aboutsummaryrefslogtreecommitdiffstats
path: root/passes
Commit message (Collapse)AuthorAgeFilesLines
...
* memory_map: Add wide port support.Marcelina Kościelnicka2021-05-251-16/+17
|
* sim: Add wide port support.Marcelina Kościelnicka2021-05-251-3/+3
|
* Reject wide ports in some passes that will never support them.Marcelina Kościelnicka2021-05-251-0/+14
|
* opt_mem_feedback: Rewrite feedback path finding logic.Marcelina Kościelnicka2021-05-241-115/+130
| | | | Fixes #2766.
* opt_mem_feedback: Convert to Mem helpers.Marcelina Kościelnicka2021-05-241-49/+28
|
* memory_share: Use Mem helpers.Marcelina Kościelnicka2021-05-231-89/+71
|
* extract_rdff: Add initvals parameter.Marcelina Kościelnicka2021-05-232-9/+15
| | | | | This is not used yet, but will be needed when read port reset/initial value support lands.
* memory_share: Split off feedback path finding as a separate pass.Marcelina Kościelnicka2021-05-234-242/+343
| | | | | memory_share is actually three passes in a trenchcoat. Split off the one that has the least in common with the other two as a separate pass.
* Add new helper class for merging FFs into cells, use for memory_dff.Marcelina Kościelnicka2021-05-231-237/+104
| | | | Fixes #1854.
* opt_mem: Remove write ports with const-0 EN.Marcelina Kościelnicka2021-05-231-0/+12
| | | | Fixes #2765.
* memory_memx: Use Mem helper.Marcelina Kościelnicka2021-05-221-42/+31
|
* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-225-24/+7
| | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list.
* memory_dff: Use Mem helper.Marcelina Kościelnicka2021-05-211-19/+26
|
* connect: Add -assert option, fix non-working sigmap.Marcelina Kościelnicka2021-05-081-4/+24
| | | | Should be useful for writing tests.
* opt_dff: Fix NOT gates wired in reverse.Marcelina Kościelnicka2021-05-041-2/+2
|
* flatten: rewrite memid in memwr actions.whitequark2021-04-091-0/+3
|
* equiv: Suggest running async2sync or clk2fflogic where appropriate.Marcelina Kościelnicka2021-03-302-3/+10
| | | | See #2713.
* abc9: uniquify blackboxes like whiteboxes (#2695)Eddie Hung2021-03-291-10/+6
| | | | | | | | | * abc9_ops: uniquify blackboxes too * abc9_ops: update comment * abc9_ops: allow bypass for param-less blackboxes * Add tests
* abc9: fix SCC issues (#2694)Eddie Hung2021-03-292-28/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
* Clarify bugpoint documentation regarding outputIris Johnson2021-03-241-0/+2
| | | | | | | Bugpoint's current documentation does specify that the result of a run is stored as the current design, however it's easy to skim over what that means in practice. Add a documentation comment to explain specifically that an after bugpoint `write_xyz` pass is required to save the reduced design.
* bugpoint: add runner optionZachary Snow2021-03-171-6/+17
|
* blackbox: Include whiteboxed modulesgatecat2021-03-171-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* proc_arst: Add special-casing of clock signal in conditionals.Marcelina Kościelnicka2021-03-151-23/+51
| | | | | | | | | | | | | | | | | The already-existing special case for conditionals on clock has been remade as follows: - now triggered for the last remaining edge trigger after all others have been converted to async reset, not just when there is only one sync rule in the first place - does not require all contained assignments to be constant, as opposed to a reset conditional — merely const-folds the condition In addition, the code has been refactored a bit; as a bonus, the priority order of async resets found is now preserved in resulting sync rule ordering (though this is not yet respected by proc_dff). Fixes #2656.
* opt_clean: Remove init attribute bits together with removed DFFs.Marcelina Kościelnicka2021-03-151-0/+4
| | | | Fixes #2546.
* Add _pm.h files to GENLIST, fixes vcxsrc targetMiodrag Milanovic2021-03-111-0/+9
|
* memory_dff: Remove now-useless write port handling.Marcelina Kościelnicka2021-03-083-74/+11
|
* Add support for memory writes in processes.Marcelina Kościelnicka2021-03-0810-37/+181
|
* sim: Avoid a crash on empty cell connection.Marcelina Kościelnicka2021-03-081-1/+1
| | | | Fixes #2513.
* proc_dff: Fix emitted FF when a register is not assigned in async resetMarcelina Kościelnicka2021-03-081-0/+4
| | | | Fixes #2619.
* memory_dff: Remove code looking for $mux cells.Marcelina Kościelnicka2021-03-081-56/+12
| | | | This job is now performed by `opt_dff`, which runs before this pass.
* Replace assert in abc9_ops with more useful error messageDan Ravensloft2021-03-071-1/+9
|
* proc_clean: Fix empty case removal conditions.Marcelina Kościelnicka2021-03-061-10/+21
| | | | Fixes #2639.
* assertpmux: Fix crash on unused $pmux output.Marcelina Kościelnicka2021-02-221-1/+1
| | | | Fixes #2595.
* Fixes command line for abc pass in -fast -sop modeRobert Baruch2021-02-161-1/+1
|
* Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-041-23/+22
|\ | | | | verilog: significant block scoping improvements
| * verilog: significant block scoping improvementsZachary Snow2021-01-311-23/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* | Merge pull request #2564 from whitequark/flatten-improve-errorwhitequark2021-01-291-1/+1
|\ \ | | | | | | flatten: clarify confusing error message
| * | flatten: clarify confusing error message.whitequark2021-01-261-1/+1
| |/
* | Merge pull request #2535 from Ravenslofty/scc-specifyClaire Xen2021-01-282-18/+61
|\ \ | |/ |/| scc: Add -specify option to find loops in boxes
| * scc: Add -specify option to find loops in boxesDan Ravensloft2021-01-262-18/+61
| |
* | Merge pull request #2549 from pgadfort/support-multiple-libswhitequark2021-01-251-15/+21
|\ \ | | | | | | adding support for passing multiple liberty files to abc
| * | adding support for passing multiple liberty files to abcPeter Gadfort2021-01-181-15/+21
| | |
* | | Merge pull request #2536 from TobiasFaller/masterMiodrag Milanović2021-01-201-0/+1
|\ \ \ | |/ / |/| | Fixed missing goto statement in passes/techmap/abc.cc
| * | Fixed missing goto statement in passes/techmap/abc.ccTobias Faller2021-01-121-0/+1
| |/
* / opt_share: Fix X and CO signal width for shifted $alu in opt_share.Marcelina Kościelnicka2021-01-141-2/+2
|/ | | | | | These need to be the same length as actual Y, not visible part of Y. Fixes #2538.
* plugin: enhance no-plugin errorumarcor2020-12-291-1/+5
|
* passes/pmgen/pmgen.py: trivial change to remove C++ compiler warningsLarry Doolittle2020-12-231-2/+2
| | | | Verified that the result still builds and passes self-tests
* Fix use-after-free in LUT opt passStefanBruens2020-12-221-2/+4
| | | | | RTLIL::Module::remove(Cell* cell) calls `delete cell`. Any subsequent accesses of `cell` then causes undefined behavior.
* Sign extend port connections where necessaryZachary Snow2020-12-182-3/+10
| | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
* Return nice error in pmgen generated code, fixes #2482Miodrag Milanovic2020-12-091-2/+6
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 08:54:21 +0000