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* | Progress in pmgenClifford Wolf2019-01-155-8/+347
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add mockup .pmg (pattern matcher generator) fileClifford Wolf2019-01-151-0/+75
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* flowmap: clean up terminology.whitequark2019-01-081-17/+18
| | | | | | | | | | * "map": group gates into LUTs; * "pack": replace gates with LUTs. This is important because we have FlowMap and DF-Map, and currently our messages are ambiguous. Also clean up some other log messages while we're at it.
* flowmap: implement depth relaxation.whitequark2019-01-087-22/+762
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* Bugfix in $memrd sharingClifford Wolf2019-01-071-2/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #782 from whitequark/flowmap_dfsClifford Wolf2019-01-073-124/+243
|\ | | | | flowmap: construct a max-volume max-flow min-cut, not just any one
| * flowmap: construct a max-volume max-flow min-cut, not just any one.whitequark2019-01-061-7/+10
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| * flowmap: add -minlut option, to allow postprocessing with opt_lut.whitequark2019-01-041-7/+21
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| * flowmap: cleanup for clarity. NFCI.whitequark2019-01-043-107/+179
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| * flowmap: improve debug graph output. NFC.whitequark2019-01-041-47/+76
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| * flowmap: add link to longer version of paper. NFC.whitequark2019-01-041-2/+3
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* | Switch "bugpoint" from system() to run_command()Clifford Wolf2019-01-071-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | bugpoint: new pass.whitequark2019-01-072-1/+370
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A typical use of `bugpoint` would involve a script with a pass under test, e.g.: flowmap -relax -optarea 100 and would be invoked as: bugpoint -yosys ./yosys -script flowmap.ys -clean -cells This replaces the current design with the minimal design that still crashes the `flowmap.ys` script. `bugpoint` can also be used to perform generic design minimization using `select`, e.g. the following script: select i:* %x t:$_MUX_ %i -assert-max 0 would remove all parts of the design except for an unbroken path from an input to an output port that goes through exactly one $_MUX_ cell. (The condition is inverted.)
* | Rename cells based on the wires they drive.Scott Mansell2019-01-061-0/+66
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* Merge pull request #775 from whitequark/opt_flowmapClifford Wolf2019-01-033-1/+875
|\ | | | | flowmap: new techmap pass
| * flowmap: new techmap pass.whitequark2019-01-033-1/+875
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* | Merge pull request #770 from whitequark/opt_expr_cmpClifford Wolf2019-01-021-97/+134
|\ \ | |/ |/| opt_expr: refactor and improve simplification of comparisons
| * opt_expr: improve simplification of comparisons with large constants.whitequark2019-01-021-70/+47
| | | | | | | | | | | | | | | | | | | | | | | | The idea behind this simplification is that a N-bit signal X being compared with an M-bit constant where M>N and the constant has Nth or higher bit set, it either always succeeds or always fails. However, the existing implementation only worked with one-hot signals for some reason. It also printed incorrect messages. This commit adjusts the simplification to have as much power as possible, and fixes other bugs.
| * opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.whitequark2019-01-021-31/+37
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| * opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.whitequark2019-01-021-24/+26
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| * opt_expr: simplify any unsigned comparisons with all-0 and all-1.whitequark2019-01-021-17/+69
| | | | | | | | | | | | Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input.
* | Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-021-3/+30
|\ \ | | | | | | Initialization of Anlogic DFFs
| * | Add "dffinit -noreinit" parameterIcenowy Zheng2018-12-181-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes the FF cell might be initialized during the map process, e.g. some FPGA platforms (Anlogic Eagle and Lattice ECP5 for example) has only a "SR" pin for a FF for async reset, that resets the FF to the initial value, which means the async reset value should be set as the initial value. In this case the DFFINIT pass shouldn't reinitialize it to a different value, which will lead to error. Add a "-noreinit" parameter for the safeguard. If a FF is not technically initialized before DFFINIT pass, the default value should be set to x. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
| * | Add "dffinit -strinit high low"Icenowy Zheng2018-12-181-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some platforms the string to initialize DFF might not be "high" and "low", e.g. with Anlogic TD it's "SET" and "RESET". Add a "-strinit" parameter for dffinit to allow specify the strings used for high and low. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | | Merge pull request #773 from whitequark/opt_lut_elim_fixesClifford Wolf2019-01-021-8/+31
|\ \ \ | | | | | | | | opt_lut: elimination fixes
| * | | opt_lut: reflect changes in sigmap.whitequark2019-01-021-0/+2
| | | | | | | | | | | | | | | | Otherwise, some LUTs will be missed during elimination.
| * | | opt_lut: use a worklist, and revisit cells affected by elimination.whitequark2019-01-021-3/+10
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| * | | opt_lut: count eliminated cells, and set opt.did_something for them.whitequark2019-01-021-6/+20
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* / | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-0211-19/+19
|/ / | | | | | | | | | | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* | opt_lut: eliminate LUTs evaluating to constants or inputs.whitequark2018-12-311-0/+81
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* | Fix handling of (* keep *) wires in wreduceClifford Wolf2018-12-311-1/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | proc_clean: remove any empty cases if all cases use all-def compare.whitequark2018-12-231-6/+28
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* | proc_clean: remove any empty cases at the end of the switch.whitequark2018-12-221-7/+3
| | | | | | | | Previously, only completely empty switches were removed.
* | memory_collect: do not truncate 'x from \INIT.whitequark2018-12-211-3/+0
| | | | | | | | | | | | | | The semantics of an RTLIL constant that has less bits than its declared bit width is zero padding. Therefore, if the output of memory_collect will be used for simulation, truncating 'x from the end of \INIT will produce incorrect simulation results.
* | memory_dff: Fix typo when checking init valueDavid Shah2018-12-181-1/+1
|/ | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Revert "Proof-of-concept: preserve naming through ABC using dress"Clifford Wolf2018-12-161-51/+29
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* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-161-8/+50
|\ | | | | select: print selection if a -assert-* flag causes an error
| * select: print selection if a -assert-* flag causes an error.whitequark2018-12-161-8/+50
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* | Merge pull request #735 from daveshah1/trifixesClifford Wolf2018-12-161-3/+4
|\ \ | | | | | | deminout fixes
| * | deminout: Consider $tribuf cellsDavid Shah2018-12-121-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | deminout: Don't demote constant-driven inouts to inputsDavid Shah2018-12-121-1/+2
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix equiv_opt indentingClifford Wolf2018-12-161-139/+129
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-162-1/+168
|\ \ | | | | | | equiv_opt: new command, for verifying optimization passes
| * | equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-071-2/+4
| | | | | | | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models.
| * | equiv_opt: new command, for verifying optimization passes.whitequark2018-12-072-1/+166
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* | | Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdataClifford Wolf2018-12-161-0/+17
|\ \ \ | | | | | | | | memory_bram: Fix initdata bit order after shuffling
| * | | memory_bram: Fix initdata bit order after shufflingGraham Edgecombe2018-12-111-0/+17
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases the memory_bram pass shuffles the order of the bits in a memory's RD_DATA port. Although the order of the bits in the WR_DATA and WR_EN ports is changed to match the RD_DATA port, the order of the bits in the initialization data is not. This causes reads of initialized memories to return invalid data (until the initialization data is overwritten). This commit fixes the bug by shuffling the initdata bits in exactly the same order as the RD_DATA/WR_DATA/WR_EN bits.
* | | Merge pull request #714 from daveshah1/abc_preserve_namingClifford Wolf2018-12-161-29/+51
|\ \ \ | | | | | | | | Proof-of-concept: preserve naming through ABC using dress
| * | | abc: Preserve naming through ABC using 'dress' commandDavid Shah2018-12-061-29/+51
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Merge pull request #722 from whitequark/rename_srcClifford Wolf2018-12-161-0/+50
|\ \ \ \ | | | | | | | | | | rename: add -src, for inferring names from source locations
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