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| * | tribuf: `-formal` option: convert all to logic and detect conflictsJannis Harder2022-04-121-3/+46
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* | | Match $anyseq input if connected to public wireMiodrag Milanovic2022-04-221-6/+12
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* | | Treat $anyseq as input from FSTMiodrag Milanovic2022-04-221-0/+21
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* | | Last sample from input does not represent changeMiodrag Milanovic2022-04-221-1/+2
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* | | latches are always set to zeroMiodrag Milanovic2022-04-221-6/+1
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* | | If not multiclock, output only on clock edgesMiodrag Milanovic2022-04-221-0/+18
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* | | Set init state for all wires from FST and set pastMiodrag Milanovic2022-04-221-13/+12
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* | | Fix multiclock for btor2 witnessMiodrag Milanovic2022-04-221-5/+9
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* | | Merge pull request #3280 from YosysHQ/micko/fix_readaiwMiodrag Milanović2022-04-181-2/+2
|\ \ \ | | | | | | | | Fix reading aiw from other solvers
| * | | Fix reading aiw from other solversMiodrag Milanovic2022-04-151-2/+2
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* | | memory_share: Fix up mismatched address widths.Marcelina Kościelnicka2022-04-151-0/+14
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* | | opt_dff: Fix behavior on $ff with D == Q.Marcelina Kościelnicka2022-04-151-1/+1
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* | Use wrap_async_control_gate if ff is fineMiodrag Milanovic2022-04-081-9/+11
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* | Makefile: properly conditionalize features requiring compression.Iris Johnson2022-04-071-0/+2
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* | Merge pull request #3269 from YosysHQ/micko/fix_autotopCatherine2022-04-071-13/+13
|\ \ | | | | | | Reorder steps in -auto-top to fix synth command, fixes #3261
| * | Reorder steps in -auto-top to fix synth command, fixes #3261Miodrag Milanovic2022-04-051-13/+13
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* | | abc: Add support for FFs with reset in -dffMarcelina Kościelnicka2022-04-071-90/+229
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* | show: Fix width labels.Marcelina Kościelnicka2022-04-041-23/+18
| | | | | | | | See #3266.
* | past_ad initial value settingMiodrag Milanovic2022-04-021-0/+3
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* | setInitState can be only one altering valuesMiodrag Milanovic2022-04-021-4/+6
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* | Set past_d value for init stateMiodrag Milanovic2022-04-021-0/+2
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* | Merge pull request #3264 from jix/invalid_ff_dcinit_mergeJannis Harder2022-04-022-2/+21
|\ \ | | | | | | opt_merge: Add `-keepdc` option required for formal verification
| * | opt_merge: Add `-keepdc` option required for formal verificationJannis Harder2022-04-012-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | The `-keepdc` option prevents merging flipflops with dont-care bits in their initial value, as, in general, this is not a valid transform for formal verification. The keepdc option of `opt` is passed along to `opt_merge` now.
* | | Set init values for wrapped async control signalsMiodrag Milanovic2022-04-011-0/+2
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* | Support memories in aiw and multiclockMiodrag Milanovic2022-03-311-16/+86
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* | Merge pull request #3194 from Ravenslofty/abc9-flow3mfsLofty2022-03-281-1/+7
|\ \ | | | | | | abc9: add flow3mfs script
| * | abc9: add flow3mfs scriptLofty2022-02-101-1/+7
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* | abc9_ops: Also derive blackboxes with timing infogatecat2022-03-241-5/+10
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
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* | Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
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* | More verbose warningsMiodrag Milanovic2022-03-181-5/+7
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* | Recognize registers and set initial state for them in tbMiodrag Milanovic2022-03-161-6/+32
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* | Update sim help message.Miodrag Milanovic2022-03-161-1/+2
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* | Merge pull request #3232 from YosysHQ/micko/fst2tbMiodrag Milanović2022-03-141-0/+319
|\ \ | | | | | | Added fst2tb pass for generating testbench
| * | Added fst2tb pass for generating testbenchMiodrag Milanovic2022-03-141-0/+319
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* | | Merge pull request #3213 from antonblanchard/abc-typoClaire Xen2022-03-141-2/+2
|\ \ \ | |/ / |/| | abc: Fix {I} and {P} substitution
| * | abc: Fix {I} and {P} substitutionAnton Blanchard2022-02-231-2/+2
| | | | | | | | | | | | We were searching for {D} after the first match of {I} or {P}.
* | | Merge pull request #3229 from YosysHQ/micko/sim_dateMiodrag Milanović2022-03-111-7/+20
|\ \ \ | | | | | | | | Add date parameter to enable full date/time and version info
| * | | Add date parameter to enable full date/time and version infoMiodrag Milanovic2022-03-111-7/+20
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* | | | Add "sim -q" optionClaire Xenia Wolf2022-03-111-8/+19
|/ / / | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | Small fix in "sim" help messageClaire Xenia Wolf2022-03-111-1/+1
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | FstData already do conversion to VCDMiodrag Milanovic2022-03-111-1/+2
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* | | Support cell name in btor witness fileMiodrag Milanovic2022-03-111-5/+14
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* | | Proper write of memory dataMiodrag Milanovic2022-03-111-14/+13
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* | | Start work on memory initMiodrag Milanovic2022-03-091-9/+34
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* | | Fixes and error checkMiodrag Milanovic2022-03-091-1/+5
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* | | cleanupMiodrag Milanovic2022-03-071-1/+2
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* | | Error checks for aiger witnessMiodrag Milanovic2022-03-071-0/+7
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* | | btor2 witness co-simulationMiodrag Milanovic2022-03-071-8/+123
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* | | Merge pull request #3219 from YosysHQ/micko/quick_vcdMiodrag Milanović2022-03-041-0/+1
|\ \ \ | | | | | | | | VCD reader support by using external tool
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