Commit message (Collapse) | Author | Age | Files | Lines | |
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* | proc_rom: Add special handling of const-0 address bits. | Marcelina Kościelnicka | 2022-05-18 | 1 | -15/+40 |
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* | opt_ffinv: Use ModIndex instead of ModWalker. | Marcelina Kościelnicka | 2022-05-17 | 1 | -50/+53 |
| | | | | This avoids using out-of-data index information. | ||||
* | Add opt_ffinv pass. | Marcelina Kościelnicka | 2022-05-13 | 2 | -0/+256 |
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* | Add proc_rom pass. | Marcelina Kościelnicka | 2022-05-13 | 3 | -0/+239 |
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* | Merge pull request #3299 from YosysHQ/mmicko/sim_memory | Miodrag Milanović | 2022-05-09 | 1 | -2/+18 |
|\ | | | | | sim pass: support for memories | ||||
| * | fix crash when no fst input | Miodrag Milanovic | 2022-05-04 | 1 | -1/+2 |
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| * | Start restoring memory state from VCD/FST | Miodrag Milanovic | 2022-05-04 | 1 | -2/+17 |
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* | | opt_mem: Remove constant-value bit lanes. | Marcelina Kościelnicka | 2022-05-07 | 1 | -13/+143 |
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* | | memory_share: fix wrong argidx in extra_args | imhcyx | 2022-05-05 | 1 | -1/+1 |
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* | | abc: Use dict/pool instead of std::map/std::set | Marcelina Kościelnicka | 2022-05-04 | 1 | -14/+14 |
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* | AIM file could have gaps in or between inputs and inits | Miodrag Milanovic | 2022-05-02 | 1 | -3/+6 |
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* | Merge pull request #3257 from jix/tribuf-formal | Jannis Harder | 2022-04-25 | 1 | -3/+46 |
|\ | | | | | tribuf: `-formal` option: convert all to logic and detect conflicts | ||||
| * | tribuf: `-formal` option: convert all to logic and detect conflicts | Jannis Harder | 2022-04-12 | 1 | -3/+46 |
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* | | Match $anyseq input if connected to public wire | Miodrag Milanovic | 2022-04-22 | 1 | -6/+12 |
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* | | Treat $anyseq as input from FST | Miodrag Milanovic | 2022-04-22 | 1 | -0/+21 |
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* | | Last sample from input does not represent change | Miodrag Milanovic | 2022-04-22 | 1 | -1/+2 |
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* | | latches are always set to zero | Miodrag Milanovic | 2022-04-22 | 1 | -6/+1 |
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* | | If not multiclock, output only on clock edges | Miodrag Milanovic | 2022-04-22 | 1 | -0/+18 |
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* | | Set init state for all wires from FST and set past | Miodrag Milanovic | 2022-04-22 | 1 | -13/+12 |
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* | | Fix multiclock for btor2 witness | Miodrag Milanovic | 2022-04-22 | 1 | -5/+9 |
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* | | Merge pull request #3280 from YosysHQ/micko/fix_readaiw | Miodrag Milanović | 2022-04-18 | 1 | -2/+2 |
|\ \ | | | | | | | Fix reading aiw from other solvers | ||||
| * | | Fix reading aiw from other solvers | Miodrag Milanovic | 2022-04-15 | 1 | -2/+2 |
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* | | memory_share: Fix up mismatched address widths. | Marcelina Kościelnicka | 2022-04-15 | 1 | -0/+14 |
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* | | opt_dff: Fix behavior on $ff with D == Q. | Marcelina Kościelnicka | 2022-04-15 | 1 | -1/+1 |
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* | Use wrap_async_control_gate if ff is fine | Miodrag Milanovic | 2022-04-08 | 1 | -9/+11 |
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* | Makefile: properly conditionalize features requiring compression. | Iris Johnson | 2022-04-07 | 1 | -0/+2 |
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* | Merge pull request #3269 from YosysHQ/micko/fix_autotop | Catherine | 2022-04-07 | 1 | -13/+13 |
|\ | | | | | Reorder steps in -auto-top to fix synth command, fixes #3261 | ||||
| * | Reorder steps in -auto-top to fix synth command, fixes #3261 | Miodrag Milanovic | 2022-04-05 | 1 | -13/+13 |
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* | | abc: Add support for FFs with reset in -dff | Marcelina Kościelnicka | 2022-04-07 | 1 | -90/+229 |
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* | show: Fix width labels. | Marcelina Kościelnicka | 2022-04-04 | 1 | -23/+18 |
| | | | | See #3266. | ||||
* | past_ad initial value setting | Miodrag Milanovic | 2022-04-02 | 1 | -0/+3 |
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* | setInitState can be only one altering values | Miodrag Milanovic | 2022-04-02 | 1 | -4/+6 |
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* | Set past_d value for init state | Miodrag Milanovic | 2022-04-02 | 1 | -0/+2 |
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* | Merge pull request #3264 from jix/invalid_ff_dcinit_merge | Jannis Harder | 2022-04-02 | 2 | -2/+21 |
|\ | | | | | opt_merge: Add `-keepdc` option required for formal verification | ||||
| * | opt_merge: Add `-keepdc` option required for formal verification | Jannis Harder | 2022-04-01 | 2 | -2/+21 |
| | | | | | | | | | | | | | | | | The `-keepdc` option prevents merging flipflops with dont-care bits in their initial value, as, in general, this is not a valid transform for formal verification. The keepdc option of `opt` is passed along to `opt_merge` now. | ||||
* | | Set init values for wrapped async control signals | Miodrag Milanovic | 2022-04-01 | 1 | -0/+2 |
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* | Support memories in aiw and multiclock | Miodrag Milanovic | 2022-03-31 | 1 | -16/+86 |
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* | Merge pull request #3194 from Ravenslofty/abc9-flow3mfs | Lofty | 2022-03-28 | 1 | -1/+7 |
|\ | | | | | abc9: add flow3mfs script | ||||
| * | abc9: add flow3mfs script | Lofty | 2022-02-10 | 1 | -1/+7 |
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* | | abc9_ops: Also derive blackboxes with timing info | gatecat | 2022-03-24 | 1 | -5/+10 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | Proper SigBit forming in sim | Miodrag Milanovic | 2022-03-22 | 1 | -4/+4 |
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* | | Proper SigBit forming in sim | Miodrag Milanovic | 2022-03-22 | 1 | -4/+4 |
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* | | More verbose warnings | Miodrag Milanovic | 2022-03-18 | 1 | -5/+7 |
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* | | Recognize registers and set initial state for them in tb | Miodrag Milanovic | 2022-03-16 | 1 | -6/+32 |
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* | | Update sim help message. | Miodrag Milanovic | 2022-03-16 | 1 | -1/+2 |
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* | | Merge pull request #3232 from YosysHQ/micko/fst2tb | Miodrag Milanović | 2022-03-14 | 1 | -0/+319 |
|\ \ | | | | | | | Added fst2tb pass for generating testbench | ||||
| * | | Added fst2tb pass for generating testbench | Miodrag Milanovic | 2022-03-14 | 1 | -0/+319 |
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* | | | Merge pull request #3213 from antonblanchard/abc-typo | Claire Xen | 2022-03-14 | 1 | -2/+2 |
|\ \ \ | |/ / |/| | | abc: Fix {I} and {P} substitution | ||||
| * | | abc: Fix {I} and {P} substitution | Anton Blanchard | 2022-02-23 | 1 | -2/+2 |
| | | | | | | | | | | | | We were searching for {D} after the first match of {I} or {P}. | ||||
* | | | Merge pull request #3229 from YosysHQ/micko/sim_date | Miodrag Milanović | 2022-03-11 | 1 | -7/+20 |
|\ \ \ | | | | | | | | | Add date parameter to enable full date/time and version info |