iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Cleanups and improvements in wreduce pass	Clifford Wolf	2014-08-05	1	-47/+77
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*	Added mux support to wreduce command	Clifford Wolf	2014-08-05	1	-36/+82
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*	Added "show -signed"	Clifford Wolf	2014-08-04	1	-5/+17
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*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04	1	-4/+3
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*	Fixed "share" for memory read ports	Clifford Wolf	2014-08-03	1	-0/+7
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*	Progress in "wreduce" pass	Clifford Wolf	2014-08-03	1	-43/+16
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*	Added "wreduce" command (work in progress)	Clifford Wolf	2014-08-03	2	-0/+253
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*	Implemented recursive techmap	Clifford Wolf	2014-08-03	1	-16/+62
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*	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03	1	-20/+18
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*	Implemented simplemap support for "techmap -extern"	Clifford Wolf	2014-08-02	1	-5/+40
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*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02	1	-0/+1
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*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02	1	-1/+1
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	8	-10/+10
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	5	-11/+13
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*	Fixed a performance bug in opt_reduce	Clifford Wolf	2014-08-02	1	-2/+6
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	26	-173/+176
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	4	-7/+7
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*	Replaced sha1 implementation	Clifford Wolf	2014-08-01	3	-13/+2
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*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	2	-6/+5
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*	Added "test_autotb -n <num_iter>" option	Clifford Wolf	2014-08-01	1	-9/+27
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*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31	2	-10/+12
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	35	-709/+709
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*	Added "trace" command	Clifford Wolf	2014-07-31	3	-2/+100
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	7	-9/+11
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	11	-15/+19
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*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31	3	-6/+6
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*	Added "techmap -assert"	Clifford Wolf	2014-07-31	2	-14/+43
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*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	1	-10/+119
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*	Added write_file command	Clifford Wolf	2014-07-30	2	-0/+77
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*	Improvements in test_cell	Clifford Wolf	2014-07-30	1	-35/+89
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*	Added "test_cell" command	Clifford Wolf	2014-07-29	2	-0/+185
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*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29	2	-0/+338
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*	Allow "hierarchy -generate" for $__ cells	Clifford Wolf	2014-07-29	1	-1/+3
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*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	2	-10/+19
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	2	-7/+11
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	25	-58/+42
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*	Added techmap -extern	Clifford Wolf	2014-07-27	1	-16/+64
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*	Added topological sorting to techmap	Clifford Wolf	2014-07-27	1	-20/+52
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*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27	1	-2/+2
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*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27	1	-1/+1
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*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27	1	-29/+54
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*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27	2	-13/+14
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*	Added log_cmd_error_expection	Clifford Wolf	2014-07-27	1	-4/+1
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	10	-87/+85
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	57	-169/+169
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	46	-117/+117
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	33	-138/+138
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	6	-74/+29
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	15	-202/+96
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*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	3	-4/+4
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