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* Merge remote-tracking branch 'origin/eddie/muxpack' into xc7muxEddie Hung2019-06-061-10/+14
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| * Fix and test for balanced caseEddie Hung2019-06-061-10/+14
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* | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7muxEddie Hung2019-06-065-2/+277
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| * Support cascading $pmux.A with $mux.A and $mux.BEddie Hung2019-06-061-17/+25
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| * More cleanupEddie Hung2019-06-061-15/+20
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| * Fix spacingEddie Hung2019-06-061-6/+5
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| * Non chain user check using next_sigEddie Hung2019-06-061-7/+5
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| * Move muxpack from passes/techmap to passes/optEddie Hung2019-06-063-1/+1
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| * Update docEddie Hung2019-06-061-4/+5
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| * Add tests, fix for !=Eddie Hung2019-06-061-9/+32
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| * Missing fileEddie Hung2019-06-061-0/+232
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| * Initial adaptation of muxpack from shregmapEddie Hung2019-06-061-0/+1
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| * Merge pull request #1071 from YosysHQ/eddie/fix_1070Clifford Wolf2019-06-061-2/+2
| |\ | | | | | | Fix typo in opt_rmdff causing register to be incorrectly removed
| | * Fix typo in opt_rmdffEddie Hung2019-06-051-2/+2
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| * | Merge pull request #1072 from YosysHQ/eddie/fix_1069Clifford Wolf2019-06-061-0/+5
| |\ \ | | | | | | | | Error out if no top module given before 'sim'
| | * | Error out if no top module given before 'sim'Eddie Hung2019-06-051-0/+5
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| * / Missing doc for -tech xilinx in shregmapEddie Hung2019-06-051-0/+3
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| * Merge pull request #1067 from YosysHQ/clifford/fix1065Eddie Hung2019-06-051-1/+1
| |\ | | | | | | Suppress driver-driver conflict warning for unknown cell types
* | | shregmap -tech xilinx_static to handle INITEddie Hung2019-06-051-22/+32
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* | | Continue support for ShregmapTechXilinx7StaticEddie Hung2019-06-051-30/+81
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* | | Add -tech xilinx_staticEddie Hung2019-06-051-2/+13
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* | | Refactor to ShregmapTechXilinx7StaticEddie Hung2019-06-051-46/+86
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* | | shregmap -tech xilinx_dynamic to work -params and -enpolEddie Hung2019-06-051-6/+26
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* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-052-27/+95
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| * | Major rewrite of wire selection in setundef -initClifford Wolf2019-06-051-30/+89
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Indent fixClifford Wolf2019-06-051-23/+25
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #999 from jakobwenzel/setundefInitFixClifford Wolf2019-06-051-16/+23
| |\ \ | | | | | | | | initialize more registers in setundef -init
| | * | initialize more registers in setundef -initJakob Wenzel2019-05-091-16/+23
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| * | | Fix typo in fmcombine log message, fixes #1063Clifford Wolf2019-06-051-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge remote-tracking branch 'origin/clifford/fix1065' into xc7muxEddie Hung2019-06-051-1/+1
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| * | | Suppress driver-driver conflict warning for unknown cell types, fixes #1065Clifford Wolf2019-06-051-1/+1
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Rename shregmap -tech xilinx -> xilinx_dynamicEddie Hung2019-06-041-4/+4
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* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-032-4/+16
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| * | Fix "tee" handling of log_streamsClifford Wolf2019-05-311-0/+5
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-4/+11
| |\ \ | | | | | | | | Do not use shiftmul peepopt pattern when mul result is truncated
| | * | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-4/+11
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Remove dupeEddie Hung2019-06-031-7/+7
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* | | | Merge branch 'xaig' into xc7muxEddie Hung2019-05-311-6/+0
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| * | | | Move clean from aigerparse to abc9Eddie Hung2019-04-231-0/+1
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| * | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-221-5/+159
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| | * \ \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-221-5/+159
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| * | | | | | Tidy upEddie Hung2019-04-221-6/+0
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* | | | | | Throw out unused code inherited from abcEddie Hung2019-05-311-212/+3
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* | | | | | Fix spellingEddie Hung2019-05-301-1/+1
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* | | | | | Revert "Re-enable &dc2"Eddie Hung2019-05-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8c58c728a79954603289abf3520139da0a9bbb26.
* | | | | | Do not double count LUT1sEddie Hung2019-05-301-1/+0
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* | | | | | Re-enable &dc2Eddie Hung2019-05-301-1/+1
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* | | | | | Reduce -W to 160Eddie Hung2019-05-291-1/+1
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* | | | | | Erase all boxes before stitchingEddie Hung2019-05-291-27/+30
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* | | | | | Call &if with -W 250Eddie Hung2019-05-291-1/+6
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