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| * | simplemap: Map `$xnor` to `$_XNOR_` cellsJannis Harder2022-11-291-15/+1
| |/ | | | | | | | | The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of the `$_XNOR_` cell.
* / Add insbuf -chain modeClaire Xenia Wolf2022-12-011-2/+38
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* sat: Add -set-def-formal option to force defined $any* outputsJannis Harder2022-11-281-6/+22
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* Support importing verilog configurations using VerificMiodrag Milanovic2022-11-251-1/+1
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* mention prerequisites in fsm_detect and fsm helpN. Engelhardt2022-11-212-0/+18
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* Rst docs conversion (#3496)KrystalDelusion2022-11-152-1/+3
| | | Rst docs conversion
* sim: Run a comb-only update step to set past values during FST cosimJannis Harder2022-11-071-12/+11
| | | | | | | | The previous approach only initialized past_d and past_ad while for FST cosim we also need to initialize the other past values like past_clk, etc. Also to properly initialize them, we need to run a combinational update step in case any of the wires feeding into the FF are private or otherwise not part of the FST.
* Add extra time at the end of a sat VCD traceClaire Xenia Wolf2022-11-011-0/+1
| | | | | | | Otherwise the final values will not show up in gtkwave waveforms when looking at the generated traces. Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Add miter -cross optionClaire Xenia Wolf2022-10-241-4/+32
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* Consistent $mux undef handlingJannis Harder2022-10-241-1/+1
| | | | | | | | | | | | | | | | | | | * Change simlib's $mux cell to use the ternary operator as $_MUX_ already does * Stop opt_expr -keepdc from changing S=x to S=0 * Change const eval of $mux and $pmux to match the updated simlib (fixes sim) * The sat behavior of $mux already matches the updated simlib The verilog frontend uses $mux for the ternary operators and this changes all interpreations of the $mux cell (that I found) to match the verilog simulation behavior for the ternary operator. For 'if' and 'case' expressions the frontend may also use $mux but uses $eqx if the verilog simulation behavior is requested with the '-ifx' option. For $pmux there is a remaining mismatch between the sat behavior and the simlib behavior. Resolving this requires more discussion, as the $pmux cell does not directly correspond to a specific verilog construct.
* Add "check -assert" to equiv_optClaire Xenia Wolf2022-10-071-1/+13
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Exclude primary inputs from quiv_make rewiringClaire Xenia Wolf2022-10-071-0/+7
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Revert "Merge pull request #641 from tklam/master"Claire Xenia Wolf2022-10-071-81/+5
| | | | | | | | | | This reverts commit 08be796cb8b1890923e459cda92211fda763f0c1, reversing changes made to 38dbb44fa0815b1fe80e68e17798aaa341d998cd. This fixes #2728. PR #641 did not actually "fix" #639. The actual issue in #639 is not equiv_make, but assumptions in equiv_simple that are not true for the test case provided in #639.
* clk2fflogic: Always correctly handle simultaneously changing signalsJannis Harder2022-10-071-103/+87
| | | | | | | | | | | | | | | | | | | | | | | | This is a complete rewrite of the FF replacing code. The previous implementation tried to implement the negative hold time by wrapping async control signals individually with pulse stretching. This did not correctly model the interaction between different simultaneously changing inputs (e.g. a falling ALOAD together with a changing AD would load the changed AD instead of the value AD had when ALOAD was high; a falling CLR could mask a raising SET for one cycle; etc.). The new approach first has the logic for all updates using only sampled values followed by the logic for all updates using only current values. That way, e.g., a falling ALOAD will load the sampled AD value but a still active ALOAD will load the current AD value. The new code also has deterministic behavior for the initial state: no operation is active when that operation would depend on a specific previous signal value. This also means clk2fflogic will no longer generate any additional uninitialized FFs. I also documented the negative hold time behavior in the help message, copying the relevant part from async2sync's help messages.
* mutate: warn if less mutations possible than number requestedN. Engelhardt2022-10-051-0/+2
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* Merge pull request #3486 from daglem/fix-flowmap-crashMiodrag Milanović2022-09-231-1/+2
|\ | | | | Fix crash in flowmap
| * Fix crash in flowmapDag Lem2022-09-201-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | In 2fcc1ee72e, the following is apparantly added in order to mark any number of undefined LUT inputs: lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size())); However this can only be done if the number of input nodes is less than minlut. This fixes #3317
* | remove extra space in formatingKamyar Mohajerani2022-09-221-2/+2
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* | stat: add tech tech-specific utilizations to jsonKamyar Mohajerani2022-09-221-65/+91
|/ | | | | - refactor resource util. estimation/calculations for Xilinx and CMOS - don't print log_header if "-json" is set
* Fix tmpdir naming when passing -nocleanup option to abc(9) on systems where ↵N. Engelhardt2022-09-132-6/+12
| | | | base_tmpdir isn't /tmp/
* Merge pull request #3458 from QuantamHD/abc_fasterN. Engelhardt2022-08-311-6/+6
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| * Improves ABC command runtime by 10-100xEthan Mahintorabi2022-08-241-6/+6
| | | | | | | | | | | | | | | | After speaking with the author of ABC he let me know that ifraig is a very old command, and that &get; &fraig -x; &put is over 100x faster than ifraig with improved PPA results. After making the change I confirmed that this is in fact a major speed up. On our internal designs in O(millions) of standard cells we saw multi hour reductions in runtime. Also included is an improvement to the dress command. Using AIG based transformations removes the spec it SATs against. Proving the input blif will make sure that no matter what commands are run the dress command can still do its job. I noticed a regression against some LUT mapping jobs that prompted me to fix this.
* | Makes sure to set initial_top when change, fixes #3462Miodrag Milanovic2022-08-261-0/+1
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* | Merge pull request #3449 from YosysHQ/aki/show_pathrwN. Engelhardt2022-08-251-0/+1
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| * | yosys: passes: cmds: show: added filename re-writing to `show -lib`Aki Van Ness2022-08-221-0/+1
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* / Fitting help messages to 80 character widthKrystalDelusion2022-08-2424-149/+157
|/ | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
* sim: -hdlname option to preserve flattened hierarchy in sim outputJannis Harder2022-08-161-9/+41
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* clk2fflogic: Generate less unused logic when using verificJannis Harder2022-08-161-1/+4
| | | | | | Verific generates a lot of FFs with an unused async load and we cannot always optimize that away before running clk2fflogic, so check for that special case here.
* rename: Add -witness modeJannis Harder2022-08-161-0/+81
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* memory_map: Add -formal optionJannis Harder2022-08-161-17/+67
| | | | | | This maps memories for a global clock based formal verification flow. This implies -keepdc, uses $ff cells for ROMs and sets hdlname attributes.
* setundef: Do not add anyseq / anyconst to unused memory port clocksJannis Harder2022-08-161-0/+24
| | | | Instead set those unused clocks to zero.
* wreduce: Keep more x-bits with -keepdcJannis Harder2022-08-161-4/+4
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* formalff: New -setundef optionJannis Harder2022-08-161-0/+335
| | | | | | | Find FFs with undefined initialization values for which changing the initialization does not change the observable behavior and initialize them. For -ff2anyinit, this reduces the number of generated $anyinit cells that drive wires with private names.
* formalff: Set new replaced_by_gclk attribute on removed dff's clksJannis Harder2022-08-161-0/+22
| | | | | | This attribute can be used by formal backends to indicate which clocks were mapped to the global clock. Update the btor and smt2 backend which already handle clock inputs to understand this attribute.
* Add the $anyinit cell and the formalff passJannis Harder2022-08-167-1/+199
| | | | | | | These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously.
* Merge pull request #3425 from YosysHQ/lofty/stat-jsonN. Engelhardt2022-08-111-38/+109
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| * stat: add option for machine-readable json outputLofty2022-08-111-38/+109
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* | Merge pull request #3277 from YosysHQ/lofty/rename-scramble_nameN. Engelhardt2022-08-111-0/+56
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| * rename: add -scramble-name option to randomly rename selectionsLofty2022-08-081-0/+56
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* | support file locations containing spacesMiodrag Milanovic2022-08-083-9/+9
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* opt_reduce: Fix use-after-free.Marcelina Kościelnicka2022-07-231-4/+2
| | | | Fixes #3418.
* sim: Fix $anyseq in nested modulesJannis Harder2022-07-221-11/+21
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* Fix external ABC build after commit 0ca0932b5.Catherine2022-07-072-4/+8
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* Merge pull request #3395 from jix/opt_dff_keepdc_initivalJannis Harder2022-07-011-5/+17
|\ | | | | opt_dff: With -keepdc, never turn undef init vals into const drivers
| * opt_dff: With -keepdc, never turn undef init vals into const driversJannis Harder2022-06-291-5/+17
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* | Merge pull request #3396 from jix/async2sync_const_clocksJannis Harder2022-07-011-0/+3
|\ \ | | | | | | async2sync: turn FFs with const clks into gclk FFs with feedback
| * | async2sync: turn FFs with const clks into gclk FFs with feedbackJannis Harder2022-06-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | The formal backends do not support multiple clocks. This includes constant clocks. Constant clocks do appear in what isn't a proper multiclock design, for example when mapping not fully initialized ROMs. As converting FFs with constant clocks to FFs using the global is doable even in a single clock flow, make async2sync do this.
* | | Merge pull request #3391 from programmerjake/simcheck-allow-smtlib2-blackboxesJannis Harder2022-07-011-7/+16
|\ \ \ | |/ / |/| | add hierarchy -smtcheck
| * | add hierarchy -smtcheckJacob Lifshay2022-06-221-7/+16
| |/ | | | | | | like -simcheck, but allow smtlib2_module modules.
* | memory_map: avoid undriven unused FF inputs for -keepdcJannis Harder2022-06-281-0/+3
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