diff options
| author | Jannis Harder <me@jix.one> | 2022-06-28 19:05:35 +0200 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-06-28 19:05:35 +0200 |
| commit | a6b440b5c9c4fb0472c01aec84961c3f1b40c954 (patch) | |
| tree | c6f1a618d352242fd6cd92d0378c53561ce300fa /passes | |
| parent | d78d807a7fa1747b40da8bac9e278183cf86d3cc (diff) | |
| download | yosys-a6b440b5c9c4fb0472c01aec84961c3f1b40c954.tar.gz yosys-a6b440b5c9c4fb0472c01aec84961c3f1b40c954.tar.bz2 yosys-a6b440b5c9c4fb0472c01aec84961c3f1b40c954.zip | |
memory_map: avoid undriven unused FF inputs for -keepdc
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/memory/memory_map.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 5ec717733..fd5b1f1ad 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -228,6 +228,9 @@ struct MemoryMapWorker data_reg_out[idx] = w_out; c->setPort(ID::Q, w_out); + + if (mem.wr_ports.empty()) + module->connect(RTLIL::SigSig(w_in, w_out)); } } |