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* Rename opt_lut.cpp to opt_lut.ccClifford Wolf2018-12-051-0/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-17/+163
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* opt_lut: always prefer to eliminate 1-LUTs.whitequark2018-12-051-19/+41
| | | | | These are always either buffers or inverters, and keeping the larger LUT preserves more source-level information about the design.
* opt_lut: collect and display statistics.whitequark2018-12-051-4/+33
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* opt_lut: refactor to use a worker. NFC.whitequark2018-12-051-170/+177
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* opt_lut: new pass, to combine LUTs for tighter packing.whitequark2018-12-052-0/+275
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* Fix typoClifford Wolf2018-12-041-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #702 from smunaut/min_ce_useClifford Wolf2018-12-041-1/+36
|\ | | | | Add option to only use DFFE is the resulting E signal would be use > N times
| * dff2dffe: Add option for unmap to only remove DFFE with low CE signal useSylvain Munaut2018-11-271-1/+36
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #676 from rafaeltp/masterClifford Wolf2018-12-011-10/+17
|\ \ | |/ |/| Splits SigSpec into bits before calling check_signal_in_fanout (solves #675)
| * using [i] to access individual bits of SigSpec and merging bits into a tmp ↵rafaeltp2018-10-211-11/+12
| | | | | | | | Sig before setting the port to new signal
| * cleaning up for PRrafaeltp2018-10-201-2/+2
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| * fixing code stylerafaeltp2018-10-201-1/+1
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| * solves #675rafaeltp2018-10-201-11/+17
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* | Add iteration limit to "opt_muxtree"Clifford Wolf2018-11-201-1/+17
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | DFFLIBMAP: changed 'missing pin' error into a warning with additional ↵Niels Moseley2018-11-061-1/+10
| | | | | | | | reason/info.
* | Allow square brackets in liberty identifiersClifford Wolf2018-11-051-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Liberty file newline handling is more relaxed. More descriptive error messageNiels Moseley2018-11-031-4/+7
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* | Report an error when a liberty file contains pin references that reference ↵Niels Moseley2018-11-031-0/+3
|/ | | | non-existing pins
* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-201-2/+5
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* Support for SystemVerilog interfaces as a port in the top level module + ↵Ruben Undheim2018-10-201-5/+36
| | | | test case
* Merge pull request #672 from daveshah1/fix_bramClifford Wolf2018-10-191-0/+1
|\ | | | | memory_bram: Reset make_outreg when growing read ports
| * memory_bram: Reset make_outreg when growing read portsDavid Shah2018-10-191-0/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-181-7/+188
|\ \ | | | | | | Support for SystemVerilog interfaces and modports
| * | Documentation improvements etc.Ruben Undheim2018-10-131-27/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
| * | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+13
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| * | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-7/+165
| |/ | | | | | | This time doing the changes mostly in AST before RTLIL generation
* | stop check_signal_in_fanout from traversing FFstklam2018-10-131-2/+2
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* | stop check_signal_in_fanout from traversing FFstklam2018-10-131-1/+12
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* | fix bug: pass by referencetklam2018-09-261-1/+1
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* | Fix issue #639TK Lam2018-09-261-0/+58
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* Merge pull request #625 from aman-goel/masterClifford Wolf2018-09-141-1/+7
|\ | | | | Minor revision to -expose in setundef pass
| * Minor revision to -expose in setundef passAman Goel2018-09-101-1/+7
| | | | | | | | Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort.
* | Fixed minor typo in "sim" help messageacw12512018-09-121-1/+1
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* | Merge pull request #606 from cr1901/show-winClifford Wolf2018-08-191-3/+20
|\ \ | |/ |/| `show` pass `-format` and `-viewer` improvements on Windows
| * Update show pass documentation with Windows caveats.William D. Jones2018-08-151-1/+2
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| * Fix run_command() when using -format and -viewer in show pass.William D. Jones2018-08-151-2/+18
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* | Revision to expose option in setundef passAman Goel2018-08-181-154/+123
| | | | | | | | | | | | Corrects indentation Simplifications and corrections
* | Merge pull request #3 from YosysHQ/masterAman Goel2018-08-18121-263/+411
|\| | | | | Updates from official repo
| * Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-15120-265/+264
| |\ | | | | | | Consistent use of 'override' for virtual methods in derived classes.
| | * Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-20120-265/+264
| | | | | | | | | | | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
| * | Add missing <deque> include (MSVC build fix)Clifford Wolf2018-07-221-0/+1
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add async2sync passClifford Wolf2018-07-192-0/+148
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #2 from YosysHQ/masterAman Goel2018-07-183-3/+155
|\| | | | | Merging with official repo
| * ecp5: Adding synchronous set/reset supportDavid Shah2018-07-143-3/+155
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Merging with official repoAman Goel2018-07-048-65/+236
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| * Add automatic verific import in hierarchy commandClifford Wolf2018-06-201-1/+19
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Be slightly less aggressive in "deminout" passClifford Wolf2018-06-191-4/+28
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Include module name for area summary statsEdmond Cote2018-06-181-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PR prints the name of the module when displaying the final area count. Pros: - Easier for the user to `grep` for area information about a specific module Cons: - Arguably more verbose, less "pretty" than author desires Verification: ~~~~ 30c30 < Chip area for this module: 20616.349000 --- > Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000 70c70 < Chip area for this module: 88.697700 --- > Chip area for module '\picorv32_axi_adapter': 88.697700 102c102 < Chip area for this module: 20705.046700 --- > Chip area for top module '\picorv32_axi': 20705.046700 ~~~~
| * Add setundef -anyseq / -anyconst support to -undriven modeClifford Wolf2018-06-011-3/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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