| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | | Entry in Makefile.inc | Eddie Hung | 2019-11-22 | 1 | -0/+1 | |
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| | * | | | | | | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -0/+268 | |
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| | | * | | | | | | New 'clkpart' to {,un}partition design according to clock/enable | Eddie Hung | 2019-11-22 | 1 | -0/+268 | |
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| | * | | | | | | | When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_ | Eddie Hung | 2019-11-21 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since they should be captured downwards from the owning flop | |||||
| | * | | | | | | | endomain -> ctrldomain | Eddie Hung | 2019-11-20 | 1 | -3/+3 | |
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| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 2 | -6/+11 | |
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| | * | | | | | | | Use "abc9_period" attribute for delay target | Eddie Hung | 2019-10-07 | 1 | -3/+24 | |
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| | * | | | | | | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 1 | -30/+6 | |
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| | * | | | | | | | Fix from merge | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
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| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-04 | 1 | -2/+12 | |
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| | * | | | | | | | | Fix merge issues | Eddie Hung | 2019-10-04 | 2 | -10/+2 | |
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| | * | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 1 | -68/+67 | |
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| | * \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-03 | 1 | -0/+14 | |
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| | * | | | | | | | | | | No need to punch ports at all | Eddie Hung | 2019-09-30 | 1 | -13/+0 | |
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| | * | | | | | | | | | | Resolve FIXME on calling proc just once | Eddie Hung | 2019-09-30 | 1 | -2/+2 | |
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| | * | | | | | | | | | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 1 | -0/+8 | |
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| | * | | | | | | | | | | Add comment | Eddie Hung | 2019-09-30 | 1 | -0/+1 | |
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| | * | | | | | | | | | | scc call on active module module only, plus cleanup | Eddie Hung | 2019-09-30 | 1 | -21/+16 | |
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| | * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 1 | -1/+1 | |
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| | * \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -3/+16 | |
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| | * | | | | | | | | | | | | Fix "scc" call inside abc9 to consider all wires | Eddie Hung | 2019-09-29 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 1 | -78/+65 | |
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| | * | | | | | | | | | | | | Split ABC9 based on clocking only, add "abc_mergeability" attr for en | Eddie Hung | 2019-09-27 | 1 | -88/+28 | |
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| | * | | | | | | | | | | | | Add -select option to aigmap | Eddie Hung | 2019-09-27 | 1 | -6/+40 | |
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| | * | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-27 | 10 | -397/+841 | |
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| | * | | | | | | | | | | | | | Revert "Remove sequential extension" | Eddie Hung | 2019-08-20 | 1 | -20/+68 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c. | |||||
| * | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor | Eddie Hung | 2019-12-30 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | Grammar | Eddie Hung | 2019-12-30 | 1 | -1/+1 | |
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| * | | | | | | | | | | | | | abc9_techmap -> _map; called from abc9 script pass along with abc9_ops | Eddie Hung | 2019-12-28 | 4 | -130/+406 | |
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| * | | | | | | | | | | | | | Rename abc9.cc -> abc9_techmap.cc | Eddie Hung | 2019-12-28 | 2 | -5/+6 | |
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| * | | | | | | | | | | / | iopadmap: Emit tristate buffers with const OE for some edge cases. | Marcin Kościelnicki | 2019-12-25 | 1 | -23/+68 | |
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| * | | | | | | | | | | | Interpret "abc9 -lut" as lut string only if [0-9:] | Eddie Hung | 2019-12-18 | 1 | -19/+18 | |
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| * | | | | | | | | | | iopadmap: Refactor and fix tristate buffer mapping. (#1527) | Marcin Kościelnicki | 2019-12-04 | 1 | -146/+97 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not). | |||||
| * | | | | | | | | | | abc9: Fix breaking of SCCs | David Shah | 2019-12-01 | 1 | -29/+40 | |
| | |_|_|_|_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | | | | | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -0/+41 | |
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| * | | | | | | | | Fix #1496. | Marcin Kościelnicki | 2019-11-18 | 1 | -4/+8 | |
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| * | | | | | | | | flowmap: when doing mincut, ensure source is always in X, not X̅. | whitequark | 2019-11-12 | 1 | -1/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1475. | |||||
| * | | | | | | | | flowmap: don't break if that creates a k+2 (and larger) LUT either. | whitequark | 2019-11-11 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1405. | |||||
| * | | | | | | | | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+12 | |
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| | * | | | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -3/+13 | |
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| * / | | | | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -65/+65 | |
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| * | | | | | Merge pull request #1422 from YosysHQ/eddie/aigmap_select | Clifford Wolf | 2019-10-03 | 1 | -6/+40 | |
| |\ \ \ \ \ | | | | | | | | | | | | | Add -select option to aigmap | |||||
| | * | | | | | Add -select option to aigmap | Eddie Hung | 2019-09-30 | 1 | -6/+40 | |
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| * | | | | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf | Eddie Hung | 2019-10-02 | 1 | -4/+8 | |
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| * | | | | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias | Eddie Hung | 2019-09-30 | 1 | -0/+10 | |
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| * | | | | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in | Miodrag Milanović | 2019-09-30 | 1 | -1/+1 | |
| |\ \ \ \ | |_|_|/ |/| | | | Open aig frontend as binary file | |||||
| | * | | | Open aig frontend as binary file | Miodrag Milanovic | 2019-09-29 | 1 | -1/+1 | |
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| * | | | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 1 | -3/+16 | |
| |\ \ \ | |/ / |/| | | DSP inference for Xilinx (improved for ice40, initial support for ecp5) | |||||
| | * | | "abc_padding" attr for blackbox outputs that were padded, remove them later | Eddie Hung | 2019-09-23 | 1 | -3/+16 | |
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| * | | | Fix _TECHMAP_REMOVEINIT_ handling. | Marcin Kościelnicki | 2019-09-27 | 1 | -13/+17 | |
| |/ / | | | | | | | | | | | | | | | Previously, this wire was handled in the code that populated the "do or do not" techmap cache, resulting in init value removal being performed only for the first use of a given template. Fixes the problem identified in #1396. | |||||
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index : iCE40/yosys | |
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