| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-02 | 2 | -11/+18 |
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| | * | Merge pull request #1601 from YosysHQ/eddie/synth_retime | Eddie Hung | 2020-01-02 | 1 | -11/+15 |
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| | | * | Revert "ABC to call retime all the time" | Eddie Hung | 2019-12-30 | 1 | -11/+15 |
| | * | | take skip wire bits into account | Miodrag Milanovic | 2020-01-01 | 1 | -0/+3 |
| | * | | Grammar | Eddie Hung | 2019-12-30 | 1 | -1/+1 |
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| * | | Update doc | Eddie Hung | 2020-01-02 | 1 | -4/+4 |
| * | | abc9 -keepff -> -dff; refactor dff operations | Eddie Hung | 2020-01-02 | 1 | -19/+30 |
| * | | Cleanup abc9, update doc for -keepff option | Eddie Hung | 2020-01-01 | 1 | -6/+5 |
| * | | Restore abc9 -keepff | Eddie Hung | 2020-01-01 | 1 | -39/+40 |
| * | | attributes.count() -> get_bool_attribute() | Eddie Hung | 2020-01-01 | 1 | -2/+2 |
| * | | parse_xaiger to not take box_lookup | Eddie Hung | 2019-12-31 | 1 | -43/+4 |
| * | | Do not re-order carry chain ports, just precompute iteration order | Eddie Hung | 2019-12-31 | 1 | -22/+0 |
| * | | Remove delay targets doc | Eddie Hung | 2019-12-30 | 1 | -9/+0 |
| * | | write_xaiger to use scratchpad for stats; cleanup abc9 | Eddie Hung | 2019-12-30 | 1 | -173/+15 |
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-30 | 1 | -23/+68 |
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| | * | iopadmap: Emit tristate buffers with const OE for some edge cases. | Marcin Kościelnicki | 2019-12-25 | 1 | -23/+68 |
| * | | Add "synth_xilinx -dff" option, cleanup abc9 | Eddie Hung | 2019-12-30 | 1 | -49/+19 |
| * | | Grammar | Eddie Hung | 2019-12-30 | 1 | -1/+1 |
| * | | Disable clock domain partitioning in Yosys pass, let ABC do it | Eddie Hung | 2019-12-23 | 1 | -6/+22 |
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 1 | -19/+18 |
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| | * | Interpret "abc9 -lut" as lut string only if [0-9:] | Eddie Hung | 2019-12-18 | 1 | -19/+18 |
| * | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t | Eddie Hung | 2019-12-19 | 1 | -5/+5 |
| * | | Remove &verify -s | Eddie Hung | 2019-12-17 | 1 | -1/+1 |
| * | | Use pool<> instead of std::set<> to preserver ordering | Eddie Hung | 2019-12-17 | 1 | -6/+6 |
| * | | Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop | Eddie Hung | 2019-12-16 | 1 | -5/+27 |
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 2 | -175/+137 |
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| | * | iopadmap: Refactor and fix tristate buffer mapping. (#1527) | Marcin Kościelnicki | 2019-12-04 | 1 | -146/+97 |
| | * | abc9: Fix breaking of SCCs | David Shah | 2019-12-01 | 1 | -29/+40 |
| * | | Call abc9 with "&write -n", and parse_xaiger() to cope | Eddie Hung | 2019-12-06 | 1 | -2/+2 |
| * | | Fix abc9 re-integration, remove abc9_control_wire, use cell->type as | Eddie Hung | 2019-12-06 | 1 | -39/+15 |
| * | | abc9 to do clock partitioning again | Eddie Hung | 2019-12-05 | 1 | -37/+144 |
| * | | Add assertion | Eddie Hung | 2019-12-03 | 1 | -0/+1 |
| * | | Add abc9_init wire, attach to abc9_flop cell | Eddie Hung | 2019-12-03 | 1 | -2/+12 |
| * | | Cleanup | Eddie Hung | 2019-12-01 | 1 | -3/+2 |
| * | | Fix debug | Eddie Hung | 2019-11-25 | 1 | -3/+3 |
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 1 | -0/+41 |
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| | * | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -0/+41 |
| * | | abc9 to contain time call | Eddie Hung | 2019-11-25 | 1 | -1/+1 |
| * | | abc9 to no longer to clock partitioning, operate on whole modules only | Eddie Hung | 2019-11-25 | 1 | -139/+32 |
| * | | Conditioning abc9 on POs not accurate due to cells | Eddie Hung | 2019-11-23 | 1 | -15/+6 |
| * | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 2 | -270/+0 |
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| | * | | Move clkpart into passes/hierarchy | Eddie Hung | 2019-11-22 | 2 | -270/+0 |
| * | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -8/+9 |
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| | * | | Only action if there is more than one clock domain | Eddie Hung | 2019-11-22 | 1 | -7/+8 |
| | * | | Replace TODO | Eddie Hung | 2019-11-22 | 1 | -1/+1 |
| * | | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 2 | -1/+2 |
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| | * | | Brackets | Eddie Hung | 2019-11-22 | 1 | -1/+1 |
| | * | | Entry in Makefile.inc | Eddie Hung | 2019-11-22 | 1 | -0/+1 |
| * | | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -0/+268 |
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| | * | | New 'clkpart' to {,un}partition design according to clock/enable | Eddie Hung | 2019-11-22 | 1 | -0/+268 |
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