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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-19/+18
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| * Interpret "abc9 -lut" as lut string only if [0-9:]Eddie Hung2019-12-181-19/+18
* | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-191-5/+5
* | Remove &verify -sEddie Hung2019-12-171-1/+1
* | Use pool<> instead of std::set<> to preserver orderingEddie Hung2019-12-171-6/+6
* | Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flopEddie Hung2019-12-161-5/+27
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-062-175/+137
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| * iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-041-146/+97
| * abc9: Fix breaking of SCCsDavid Shah2019-12-011-29/+40
* | Call abc9 with "&write -n", and parse_xaiger() to copeEddie Hung2019-12-061-2/+2
* | Fix abc9 re-integration, remove abc9_control_wire, use cell->type asEddie Hung2019-12-061-39/+15
* | abc9 to do clock partitioning againEddie Hung2019-12-051-37/+144
* | Add assertionEddie Hung2019-12-031-0/+1
* | Add abc9_init wire, attach to abc9_flop cellEddie Hung2019-12-031-2/+12
* | CleanupEddie Hung2019-12-011-3/+2
* | Fix debugEddie Hung2019-11-251-3/+3
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-251-0/+41
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| * clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-0/+41
* | abc9 to contain time callEddie Hung2019-11-251-1/+1
* | abc9 to no longer to clock partitioning, operate on whole modules onlyEddie Hung2019-11-251-139/+32
* | Conditioning abc9 on POs not accurate due to cellsEddie Hung2019-11-231-15/+6
* | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-222-270/+0
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| * | Move clkpart into passes/hierarchyEddie Hung2019-11-222-270/+0
* | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-221-8/+9
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| * | Only action if there is more than one clock domainEddie Hung2019-11-221-7/+8
| * | Replace TODOEddie Hung2019-11-221-1/+1
* | | Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-222-1/+2
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| * | BracketsEddie Hung2019-11-221-1/+1
| * | Entry in Makefile.incEddie Hung2019-11-221-0/+1
* | | Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-221-0/+268
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| * | New 'clkpart' to {,un}partition design according to clock/enableEddie Hung2019-11-221-0/+268
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* | When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_Eddie Hung2019-11-211-1/+1
* | endomain -> ctrldomainEddie Hung2019-11-201-3/+3
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-192-6/+11
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| * Fix #1496.Marcin Kościelnicki2019-11-181-4/+8
| * flowmap: when doing mincut, ensure source is always in X, not X̅.whitequark2019-11-121-1/+2
| * flowmap: don't break if that creates a k+2 (and larger) LUT either.whitequark2019-11-111-1/+1
| * Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-041-3/+12
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* | | Use "abc9_period" attribute for delay targetEddie Hung2019-10-071-3/+24
* | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-051-30/+6
* | | Fix from mergeEddie Hung2019-10-041-1/+1
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-041-2/+12
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| * | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-3/+13
* | | Fix merge issuesEddie Hung2019-10-042-10/+2
* | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-041-68/+67
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| * | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-65/+65
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-031-0/+14
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| * Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-6/+40
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| | * Add -select option to aigmapEddie Hung2019-09-301-6/+40
| * | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8