iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	1	-3/+5
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-18/+18
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01	1	-6/+1
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-1/+1
*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31	1	-2/+2
*	Added "techmap -assert"	Clifford Wolf	2014-07-31	1	-13/+42
*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	1	-10/+119
*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	1	-7/+16
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-4/+3
*	Added techmap -extern	Clifford Wolf	2014-07-27	1	-16/+64
*	Added topological sorting to techmap	Clifford Wolf	2014-07-27	1	-20/+52
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-10/+10
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-11/+11
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-5/+5
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-8/+8
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-6/+4
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-9/+9
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-9/+9
*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26	1	-8/+4
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-16/+21
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-8/+9
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-9/+9
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-9/+9
*	Added call_on_selection() and call_on_module() API	Clifford Wolf	2014-07-20	1	-9/+1
*	Added support for "blackbox" attribute to flatten/techmap	Clifford Wolf	2014-07-17	1	-1/+4
*	be more verbose when techmap yielded processes	Johann Glaser	2014-05-26	1	-1/+5
*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13	1	-0/+1
*	- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...	Siesh1oo	2014-03-12	1	-1/+2
*	Added techmap -max_iter option	Clifford Wolf	2014-03-06	1	-0/+10
*	Added _TECHMAP_REPLACE_ feature to techmap	Clifford Wolf	2014-02-20	1	-4/+21
*	Added techmap support for _TECHMAP_CONNMAP_*_	Clifford Wolf	2014-02-18	1	-0/+39
*	Better preserve wires when flattening (in comparison to techmap)	Clifford Wolf	2014-02-17	1	-12/+12
*	Added some additional checks to techmap	Clifford Wolf	2014-02-16	1	-0/+14
*	Added CONSTMSK and CONSTVAL feature to techmap	Clifford Wolf	2014-02-16	1	-0/+23
*	Added recursion support to techmap	Clifford Wolf	2014-02-16	1	-260/+262
*	Changed techmap description from "simple" to "generic"	Clifford Wolf	2014-02-06	1	-1/+1
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	1	-1/+1
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-15/+3
*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24	1	-3/+34
*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24	1	-2/+8
*	Added techmap -D and -I options	Clifford Wolf	2013-11-24	1	-2/+16
*	Added "techmap -share_map" option	Clifford Wolf	2013-11-24	1	-0/+9
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	1	-1/+1
*	Fixed "flatten" top-module detection: Only use on fully selected designs	Clifford Wolf	2013-11-24	1	-3/+4
*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24	1	-3/+26
*	Improved handling of techmap special wires	Clifford Wolf	2013-11-23	1	-1/+3
*	Added more generic _TECHMAP_ wire mechanism to techmap pass	Clifford Wolf	2013-11-23	1	-77/+185