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author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 05:03:43 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 05:03:43 +0100 |
commit | 28093d9dd288484daa9df17585c1c9f174498359 (patch) | |
tree | 3940c6d3bd95f7c983c76cd6e54bd04216867f3d /passes/techmap/techmap.cc | |
parent | a4edecb0cae0524b6f42d1a2c64af5a940c67a2f (diff) | |
download | yosys-28093d9dd288484daa9df17585c1c9f174498359.tar.gz yosys-28093d9dd288484daa9df17585c1c9f174498359.tar.bz2 yosys-28093d9dd288484daa9df17585c1c9f174498359.zip |
Added "top" attribute to mark top module in hierarchy
Diffstat (limited to 'passes/techmap/techmap.cc')
-rw-r--r-- | passes/techmap/techmap.cc | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index e273769d1..7e3ba23ec 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -500,19 +500,42 @@ struct FlattenPass : public Pass { for (auto &it : design->modules) celltypeMap[it.first].insert(it.first); + RTLIL::Module *top_mod = NULL; + for (auto &mod_it : design->modules) + if (mod_it.second->get_bool_attribute("\\top")) + top_mod = mod_it.second; + bool did_something = true; std::set<RTLIL::Cell*> handled_cells; while (did_something) { did_something = false; - for (auto &mod_it : design->modules) - if (techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true)) + if (top_mod != NULL) { + if (techmap_module(design, top_mod, design, handled_cells, celltypeMap, true)) did_something = true; + } else { + for (auto &mod_it : design->modules) + if (techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true)) + did_something = true; + } } log("No more expansions possible.\n"); + + if (top_mod != NULL) { + std::map<RTLIL::IdString, RTLIL::Module*> new_modules; + for (auto &mod_it : design->modules) + if (mod_it.second == top_mod) { + new_modules[mod_it.first] = mod_it.second; + } else { + log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first)); + delete mod_it.second; + } + design->modules.swap(new_modules); + } + techmap_cache.clear(); techmap_do_cache.clear(); log_pop(); } } FlattenPass; - + |