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techmap
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techmap.cc
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Author
Age
Files
Lines
...
*
Fixed techmap processes error msg
Clifford Wolf
2015-07-18
1
-2
/
+3
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
1
-3
/
+3
*
Improved "flatten" handlings of inout ports
Clifford Wolf
2015-05-23
1
-2
/
+26
*
Improved attributes API and handling of "src" attributes
Clifford Wolf
2015-04-24
1
-0
/
+13
*
techmap code cleanup
Clifford Wolf
2015-04-09
1
-10
/
+6
*
Added support for "file names with blanks"
Clifford Wolf
2015-04-08
1
-4
/
+2
*
Removed "techmap -share_map" (use "-map +/filename" instead)
Clifford Wolf
2015-04-08
1
-9
/
+0
*
Added "keep_hierarchy" attribute
Clifford Wolf
2015-02-25
1
-14
/
+51
*
Fixed "flatten" for non-pre-derived modules
Clifford Wolf
2015-02-21
1
-2
/
+2
*
Catch constants assigned to cell outputs in "flatten"
Clifford Wolf
2015-02-21
1
-0
/
+6
*
Added support for memories to flatten (techmap)
Clifford Wolf
2015-01-17
1
-3
/
+22
*
Fixed handling of foo.__TECHMAP_...
Clifford Wolf
2015-01-15
1
-1
/
+1
*
Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
1
-4
/
+4
*
Improvements in simplemap api, added $ne $nex $eq $eqx support
Clifford Wolf
2014-12-24
1
-3
/
+1
*
Improved TopoSort determinism
Clifford Wolf
2014-11-07
1
-1
/
+1
*
Added format __attribute__ to stringf()
Clifford Wolf
2014-10-10
1
-2
/
+4
*
Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
1
-5
/
+5
*
namespace Yosys
Clifford Wolf
2014-09-27
1
-2
/
+10
*
Fixed techmap_wrap for techmap_celltype
Clifford Wolf
2014-09-14
1
-9
/
+16
*
Added techmap_wrap attribute
Clifford Wolf
2014-09-14
1
-5
/
+28
*
Added 'techmap_maccmap' techmap attribute
Clifford Wolf
2014-09-07
1
-19
/
+53
*
Added "techmap -autoproc"
Clifford Wolf
2014-09-01
1
-2
/
+18
*
Only call proc_share_dirname() in techmap when necessary
Clifford Wolf
2014-08-23
1
-2
/
+1
*
Changed frontend-api from FILE to std::istream
Clifford Wolf
2014-08-23
1
-7
/
+6
*
Renamed toposort.h to utils.h
Clifford Wolf
2014-08-17
1
-1
/
+1
*
More idstring sort_by_* helpers and fixed tpl ordering in techmap
Clifford Wolf
2014-08-15
1
-3
/
+3
*
document "techmap -map %<design-name>"
Clifford Wolf
2014-08-15
1
-0
/
+3
*
Implemented recursive techmap
Clifford Wolf
2014-08-03
1
-16
/
+62
*
Implemented simplemap support for "techmap -extern"
Clifford Wolf
2014-08-02
1
-5
/
+40
*
Bugfix in "techmap -extern"
Clifford Wolf
2014-08-02
1
-0
/
+1
*
No implicit conversion from IdString to anything else
Clifford Wolf
2014-08-02
1
-1
/
+1
*
More bugfixes related to new RTLIL::IdString
Clifford Wolf
2014-08-02
1
-3
/
+5
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
1
-18
/
+18
*
Replaced sha1 implementation
Clifford Wolf
2014-08-01
1
-6
/
+1
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
1
-1
/
+1
*
Renamed "stdcells.v" to "techmap.v"
Clifford Wolf
2014-07-31
1
-2
/
+2
*
Added "techmap -assert"
Clifford Wolf
2014-07-31
1
-13
/
+42
*
Added techmap CONSTMAP feature
Clifford Wolf
2014-07-30
1
-10
/
+119
*
Added "techmap -map %{design-name}"
Clifford Wolf
2014-07-29
1
-7
/
+16
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
1
-4
/
+3
*
Added techmap -extern
Clifford Wolf
2014-07-27
1
-16
/
+64
*
Added topological sorting to techmap
Clifford Wolf
2014-07-27
1
-20
/
+52
*
Using new obj iterator API in a few places
Clifford Wolf
2014-07-27
1
-10
/
+10
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
1
-11
/
+11
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
1
-5
/
+5
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
1
-8
/
+8
*
Changed more code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
1
-6
/
+4
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
1
-1
/
+1
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
1
-9
/
+9
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-9
/
+9
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