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* Use more ID::{A,B,Y,blackbox,whitebox}Eddie Hung2019-08-151-60/+60
* ID(\\.*) -> ID(.*)Eddie Hung2019-08-151-163/+163
* Transform all "\\*" identifiers into ID()Eddie Hung2019-08-151-163/+163
* Transform "$.*" to ID("$.*") in passes/techmapEddie Hung2019-08-151-68/+68
* Use State::S{0,1}Eddie Hung2019-08-061-1/+1
* Make liberal use of IdString.in()Eddie Hung2019-08-061-1/+1
* Check blackbox attribute in techmap/simplemapClifford Wolf2019-04-201-1/+1
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Added $ff and $_FF_ cell typesClifford Wolf2016-10-121-1/+19
* Improved support for $sop cellsClifford Wolf2016-06-171-0/+31
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Bugfix in mapping $tribuf to $_TBUF_Clifford Wolf2015-11-051-1/+1
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
* Added $tribuf and $_TBUF_ cell typesClifford Wolf2015-08-161-1/+17
* Fixed trailing whitespacesClifford Wolf2015-07-021-6/+6
* Added simplemap $lut supportClifford Wolf2015-04-271-0/+24
* Improved attributes API and handling of "src" attributesClifford Wolf2015-04-241-4/+22
* Fixed simplemap for $ne cells with output width > 1Clifford Wolf2014-12-251-7/+8
* Improvements in simplemap api, added $ne $nex $eq $eqx supportClifford Wolf2014-12-241-23/+58
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
* Added $dffe cell typeClifford Wolf2014-12-081-0/+23
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-9/+9
* namespace YosysClifford Wolf2014-09-271-1/+11
* Removed $bu0 cell typeClifford Wolf2014-09-041-12/+1
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-4/+4
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-3/+3
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-85/+85
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
* Using new obj iterator API in a few placesClifford Wolf2014-07-271-11/+9
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-5/+5
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-99/+99
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-99/+99
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-60/+16
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-98/+45
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-56/+56
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-56/+56
* Removed deprecated module->new_wire()Clifford Wolf2014-07-211-4/+4
* Added $slice and $concat cell typesClifford Wolf2014-02-071-0/+18
* Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)Clifford Wolf2013-12-291-2/+2
* Added new cell types to manualClifford Wolf2013-12-281-1/+1
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-281-0/+13
* Using simplemap mappers from techmapClifford Wolf2013-11-241-25/+30
* Added simplemap passClifford Wolf2013-11-241-0/+517