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* Merge pull request #1767 from YosysHQ/eddie/idstringsEddie Hung2020-04-021-4/+4
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| * kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-4/+4
* | iopadmap: Fix z assignment to inout portMarcin Kościelnicki2020-04-021-1/+15
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* iopadmap: Attempt to give new wires/cells meaningful namesR. Ou2020-03-221-6/+18
* iopadmap: Look harder for already-present buffers. (#1731)Marcelina Kościelnicka2020-03-021-14/+54
* iopadmap: fixes as suggested by @mwkmwkmwkEddie Hung2020-02-131-19/+11
* iopadmap: move \init attributes from outpad output to its inputEddie Hung2020-02-131-3/+20
* take skip wire bits into accountMiodrag Milanovic2020-01-011-0/+3
* iopadmap: Emit tristate buffers with const OE for some edge cases.Marcin Kościelnicki2019-12-251-23/+68
* iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-041-146/+97
* Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-6/+6
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| * Use ID::keep more liberally tooEddie Hung2019-08-151-4/+4
| * Use more ID::{A,B,Y,blackbox,whitebox}Eddie Hung2019-08-151-2/+2
* | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-161-8/+8
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| * ID(\\.*) -> ID(.*)Eddie Hung2019-08-151-7/+7
| * Transform all "\\*" identifiers into ID()Eddie Hung2019-08-151-7/+7
| * Transform "$.*" to ID("$.*") in passes/techmapEddie Hung2019-08-151-1/+1
* | move attributes to wiresMarcin Kościelnicki2019-08-131-9/+4
* | review fixesMarcin Kościelnicki2019-08-131-14/+1
* | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-131-20/+56
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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Fix iopadmap for loops between tristate IO buffersClifford Wolf2018-05-151-0/+21
* Fix iopadmap for cases where IO pins already have buffers on themClifford Wolf2018-05-151-1/+35
* Undo "preserve wire attributes in iopadmap" change (it was OK before)Clifford Wolf2016-08-081-1/+1
* preserve wire attributes in iopadmapClifford Wolf2016-08-061-1/+1
* Added tristate buffer support to iopadmapClifford Wolf2016-05-041-4/+161
* Fixed iopadmap attribute handlingClifford Wolf2016-05-041-0/+1
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Fixed iopadmap help messageClifford Wolf2015-08-311-3/+3
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Bugfix in iopadmapClifford Wolf2015-02-251-10/+3
* Various small improvements to synth_xilinxClifford Wolf2015-01-061-2/+2
* namespace YosysClifford Wolf2014-09-271-1/+5
* Bugfix in iopadmapClifford Wolf2014-08-151-1/+3
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-4/+4
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-7/+2
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+4
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-4/+4
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-4/+4
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-8/+2
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-2/+2
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-2/+2
* Added support for "blackbox" attribute to iopadmapClifford Wolf2014-07-171-1/+1
* Added iopadmap -bitsClifford Wolf2014-02-151-14/+48
* Added support for i/o buffers to iopadmapClifford Wolf2013-10-261-10/+35
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-241-1/+1
* Added iopadmap passClifford Wolf2013-10-161-0/+159