| Commit message (Expand) | Author | Age | Files | Lines |
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| * | iopadmap: Fix z assignment removal. | Marcelina Kościelnicka | 2022-06-07 | 1 | -7/+21 |
| * | Correct a typo in the manual | YRabbit | 2022-02-02 | 1 | -1/+1 |
| * | iopadmap: Fix ebmarassing typo | Marcelina Kościelnicka | 2021-11-10 | 1 | -1/+1 |
| * | iopadmap: Add native support for negative-polarity output enable. | Marcelina Kościelnicka | 2021-11-09 | 1 | -7/+22 |
| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
| * | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 1 | -2/+2 |
| * | Merge pull request #1767 from YosysHQ/eddie/idstrings | Eddie Hung | 2020-04-02 | 1 | -4/+4 |
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| | * | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -4/+4 |
| * | | iopadmap: Fix z assignment to inout port | Marcin Kościelnicki | 2020-04-02 | 1 | -1/+15 |
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| * | iopadmap: Attempt to give new wires/cells meaningful names | R. Ou | 2020-03-22 | 1 | -6/+18 |
| * | iopadmap: Look harder for already-present buffers. (#1731) | Marcelina Kościelnicka | 2020-03-02 | 1 | -14/+54 |
| * | iopadmap: fixes as suggested by @mwkmwkmwk | Eddie Hung | 2020-02-13 | 1 | -19/+11 |
| * | iopadmap: move \init attributes from outpad output to its input | Eddie Hung | 2020-02-13 | 1 | -3/+20 |
| * | take skip wire bits into account | Miodrag Milanovic | 2020-01-01 | 1 | -0/+3 |
| * | iopadmap: Emit tristate buffers with const OE for some edge cases. | Marcin Kościelnicki | 2019-12-25 | 1 | -23/+68 |
| * | iopadmap: Refactor and fix tristate buffer mapping. (#1527) | Marcin Kościelnicki | 2019-12-04 | 1 | -146/+97 |
| * | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -6/+6 |
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| | * | Use ID::keep more liberally too | Eddie Hung | 2019-08-15 | 1 | -4/+4 |
| | * | Use more ID::{A,B,Y,blackbox,whitebox} | Eddie Hung | 2019-08-15 | 1 | -2/+2 |
| * | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-16 | 1 | -8/+8 |
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| | * | ID(\\.*) -> ID(.*) | Eddie Hung | 2019-08-15 | 1 | -7/+7 |
| | * | Transform all "\\*" identifiers into ID() | Eddie Hung | 2019-08-15 | 1 | -7/+7 |
| | * | Transform "$.*" to ID("$.*") in passes/techmap | Eddie Hung | 2019-08-15 | 1 | -1/+1 |
| * | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 1 | -9/+4 |
| * | | review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -14/+1 |
| * | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 1 | -20/+56 |
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| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| * | Fix iopadmap for loops between tristate IO buffers | Clifford Wolf | 2018-05-15 | 1 | -0/+21 |
| * | Fix iopadmap for cases where IO pins already have buffers on them | Clifford Wolf | 2018-05-15 | 1 | -1/+35 |
| * | Undo "preserve wire attributes in iopadmap" change (it was OK before) | Clifford Wolf | 2016-08-08 | 1 | -1/+1 |
| * | preserve wire attributes in iopadmap | Clifford Wolf | 2016-08-06 | 1 | -1/+1 |
| * | Added tristate buffer support to iopadmap | Clifford Wolf | 2016-05-04 | 1 | -4/+161 |
| * | Fixed iopadmap attribute handling | Clifford Wolf | 2016-05-04 | 1 | -0/+1 |
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
| * | Fixed iopadmap help message | Clifford Wolf | 2015-08-31 | 1 | -3/+3 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
| * | Bugfix in iopadmap | Clifford Wolf | 2015-02-25 | 1 | -10/+3 |
| * | Various small improvements to synth_xilinx | Clifford Wolf | 2015-01-06 | 1 | -2/+2 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -1/+5 |
| * | Bugfix in iopadmap | Clifford Wolf | 2014-08-15 | 1 | -1/+3 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -4/+4 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -7/+2 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -4/+4 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -4/+4 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -4/+4 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -8/+2 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 1 | -2/+2 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 | 1 | -2/+2 |
