| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| * | Fix iopadmap for loops between tristate IO buffers | Clifford Wolf | 2018-05-15 | 1 | -0/+21 |
| * | Fix iopadmap for cases where IO pins already have buffers on them | Clifford Wolf | 2018-05-15 | 1 | -1/+35 |
| * | Undo "preserve wire attributes in iopadmap" change (it was OK before) | Clifford Wolf | 2016-08-08 | 1 | -1/+1 |
| * | preserve wire attributes in iopadmap | Clifford Wolf | 2016-08-06 | 1 | -1/+1 |
| * | Added tristate buffer support to iopadmap | Clifford Wolf | 2016-05-04 | 1 | -4/+161 |
| * | Fixed iopadmap attribute handling | Clifford Wolf | 2016-05-04 | 1 | -0/+1 |
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
| * | Fixed iopadmap help message | Clifford Wolf | 2015-08-31 | 1 | -3/+3 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
| * | Bugfix in iopadmap | Clifford Wolf | 2015-02-25 | 1 | -10/+3 |
| * | Various small improvements to synth_xilinx | Clifford Wolf | 2015-01-06 | 1 | -2/+2 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -1/+5 |
| * | Bugfix in iopadmap | Clifford Wolf | 2014-08-15 | 1 | -1/+3 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -4/+4 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -7/+2 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -4/+4 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -4/+4 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -4/+4 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -8/+2 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 1 | -2/+2 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 | 1 | -2/+2 |
| * | Added support for "blackbox" attribute to iopadmap | Clifford Wolf | 2014-07-17 | 1 | -1/+1 |
| * | Added iopadmap -bits | Clifford Wolf | 2014-02-15 | 1 | -14/+48 |
| * | Added support for i/o buffers to iopadmap | Clifford Wolf | 2013-10-26 | 1 | -10/+35 |
| * | Fixed handling of boolean attributes (passes) | Clifford Wolf | 2013-10-24 | 1 | -1/+1 |
| * | Added iopadmap pass | Clifford Wolf | 2013-10-16 | 1 | -0/+159 |
