iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	1	-3/+3
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-2/+1
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-6/+6
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-3/+3
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-3/+3
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-4/+1
*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	1	-2/+2
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-3/+5
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-12/+12
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-12/+12
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-10/+3
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-33/+24
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-3/+3
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-1/+1
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-1/+1
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-12/+12
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-12/+12
*	Added "extract -ignore_parameters" and "extract -ignore_param ..."	Clifford Wolf	2014-02-20	1	-0/+79
*	Added "extract -map %<design_name>"	Clifford Wolf	2014-02-20	1	-10/+30
*	Moved some passes to other source directories	Clifford Wolf	2014-02-08	1	-0/+680