index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
passes
/
techmap
/
dfflibmap.cc
Commit message (
Expand
)
Author
Age
Files
Lines
*
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
Clifford Wolf
2014-03-11
1
-0
/
+1
*
Fixed dfflibmap for cell libraries with no set-reset-ff
Clifford Wolf
2014-02-15
1
-1
/
+1
*
renamed LibertyParer to LibertyParser
Clifford Wolf
2014-01-14
1
-1
/
+1
*
Fixed dfflibmap for unused output ports
Clifford Wolf
2013-12-21
1
-0
/
+1
*
Now prefer smallest cells in dfflibmap
Clifford Wolf
2013-12-21
1
-2
/
+22
*
Cleanup of dfflibmap cellmap exploration code
Clifford Wolf
2013-12-20
1
-17
/
+20
*
Further improved dfflibmap cellmap exploration
Clifford Wolf
2013-12-20
1
-14
/
+18
*
Fixed dfflibmap endless-loop bug
Clifford Wolf
2013-12-20
1
-0
/
+1
*
Prefer non-inverted clocks in dfflibmap
Clifford Wolf
2013-12-19
1
-6
/
+8
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
1
-1
/
+1
*
Added placeholder check to dfflibmap and cleaned up some other placeholder ch...
Clifford Wolf
2013-10-31
1
-1
/
+1
*
Added support for sr flip-flops to dfflibmap
Clifford Wolf
2013-10-24
1
-3
/
+168
*
Moved dfflibmap from passes/dfflibmap to passes/techmap
Clifford Wolf
2013-10-16
1
-0
/
+342