iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Expand)	Author	Age	Files	Lines
*	ABC -> ABC9	Eddie Hung	2019-02-20	1	-1/+1
*	abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_	Eddie Hung	2019-02-20	1	-21/+29
*	lut/not/and suffix to be ${lut,not,and}	Eddie Hung	2019-02-20	1	-4/+4
*	abc9 to cope with multiple modules	Eddie Hung	2019-02-20	1	-7/+11
*	abc9 to use & syntax for -fast, and name fixes	Eddie Hung	2019-02-20	1	-5/+5
*	abc9 to cope with indexed wires when creating $lut from $_NOT_	Eddie Hung	2019-02-19	1	-1/+6
*	abc9 to replace $_NOT_ with $lut	Eddie Hung	2019-02-19	1	-4/+39
*	Get rid of debugging stuff in abc9	Eddie Hung	2019-02-16	1	-6/+1
*	abc9 to write_aiger with -O option, and ignore dummy outputs	Eddie Hung	2019-02-16	1	-2/+8
*	abc9 to handle comb loops, cope with constant outputs, disconnect using new wire	Eddie Hung	2019-02-16	1	-4/+67
*	abc9 to cope with non-wideports, count cells properly	Eddie Hung	2019-02-16	1	-11/+54
*	Move lookup inside if	Eddie Hung	2019-02-15	1	-2/+2
*	Refactor	Eddie Hung	2019-02-15	1	-29/+32
*	Cope with width != 1 when re-mapping cells	Eddie Hung	2019-02-15	1	-11/+25
*	abc9 to stitch results with CI/CO properly	Eddie Hung	2019-02-15	1	-16/+32
*	Fix stitching	Eddie Hung	2019-02-13	1	-4/+4
*	Rip out some more stuff	Eddie Hung	2019-02-13	1	-36/+0
*	Rip out unused functions in abc9	Eddie Hung	2019-02-12	1	-416/+61
*	WIP for ABC with aiger	Eddie Hung	2019-02-12	1	-130/+19
*	Compile abc9	Eddie Hung	2019-02-08	1	-8/+8
*	Copy abc.cc to abc9.cc	Eddie Hung	2019-02-08	1	-0/+1868