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* substr() -> compare()Eddie Hung2019-08-071-2/+2
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* Use State::S{0,1}Eddie Hung2019-08-061-1/+1
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* Add "techmap -wb", use in formal flowsClifford Wolf2019-04-201-4/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Bugfix in "miter -assert" handling of assumptionsClifford Wolf2016-10-171-2/+2
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* Added $ff and $_FF_ cell typesClifford Wolf2016-10-121-7/+31
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* Added "yosys -D" featureClifford Wolf2016-04-211-2/+2
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* Renamed opt_const to opt_exprClifford Wolf2016-03-311-4/+4
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* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
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* Added "miter -assert"Clifford Wolf2015-07-251-1/+93
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* Fixed trailing whitespacesClifford Wolf2015-07-021-4/+4
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* namespace YosysClifford Wolf2014-09-271-1/+5
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* Use "-keepdc" in "miter -equiv -flatten"Clifford Wolf2014-08-071-2/+2
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* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-021-3/+3
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-28/+28
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* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-311-1/+1
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-6/+6
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-7/+7
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-18/+5
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* Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+4
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-29/+29
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-29/+29
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-41/+10
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-1/+1
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-1/+1
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* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-4/+4
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-4/+4
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* Removed deprecated module->new_wire()Clifford Wolf2014-07-211-6/+6
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* Added "miter -equiv -flatten"Clifford Wolf2014-07-201-0/+14
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* added log_header to miter and expose pass, show cell type for exposed portsJohann Glaser2014-05-281-0/+4
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* Added miter -make_outcmpClifford Wolf2014-02-061-2/+23
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* Fixed a bug in miter commandClifford Wolf2014-02-011-2/+2
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* Added miter commandClifford Wolf2014-02-011-0/+306