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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 19:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | a233762a815fc180b371f699e865a7d7aed77bca (patch) | |
| tree | 722e54921bbc09595c046c6045cd531445945fc9 /passes/sat/miter.cc | |
| parent | 3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff) | |
| download | yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.gz yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.bz2 yosys-a233762a815fc180b371f699e865a7d7aed77bca.zip | |
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'passes/sat/miter.cc')
| -rw-r--r-- | passes/sat/miter.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 6e57fceb1..1cd794b56 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -253,11 +253,11 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, } } - if (all_conditions.width != 1) { + if (all_conditions.__width != 1) { RTLIL::Cell *reduce_cell = new RTLIL::Cell; reduce_cell->name = NEW_ID; reduce_cell->type = "$reduce_and"; - reduce_cell->parameters["\\A_WIDTH"] = all_conditions.width; + reduce_cell->parameters["\\A_WIDTH"] = all_conditions.__width; reduce_cell->parameters["\\Y_WIDTH"] = 1; reduce_cell->parameters["\\A_SIGNED"] = 0; reduce_cell->connections["\\A"] = all_conditions; @@ -283,8 +283,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL::Cell *not_cell = new RTLIL::Cell; not_cell->name = NEW_ID; not_cell->type = "$not"; - not_cell->parameters["\\A_WIDTH"] = all_conditions.width; - not_cell->parameters["\\A_WIDTH"] = all_conditions.width; + not_cell->parameters["\\A_WIDTH"] = all_conditions.__width; + not_cell->parameters["\\A_WIDTH"] = all_conditions.__width; not_cell->parameters["\\Y_WIDTH"] = w_trigger->width; not_cell->parameters["\\A_SIGNED"] = 0; not_cell->connections["\\A"] = all_conditions; |