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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* Add #include needed to build with gcc-11Gabriel Somlo2020-11-261-0/+1
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-1/+1
* kernel: use more ID::*Eddie Hung2020-04-021-4/+4
* Further clean up `passes/sat/freduce.cc`.Alberto Gonzalez2020-03-301-3/+2
* Clean up pseudo-private member usage in `passes/sat/freduce.cc`.Alberto Gonzalez2020-03-281-13/+12
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Add "setundef -anyseq"Clifford Wolf2017-05-281-1/+2
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-5/+5
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Added logic-loop error handling to freduceClifford Wolf2015-06-301-0/+11
* Replaced ezDefaultSAT with ezSatPtrClifford Wolf2015-02-211-27/+27
* namespace YosysClifford Wolf2014-09-271-3/+3
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-2/+2
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-3/+3
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-7/+7
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-7/+7
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-4/+1
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-5/+5
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-1/+1
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-1/+1
* Removed deprecated module->new_wire()Clifford Wolf2014-07-211-2/+2
* Fixed bug in freduce commandClifford Wolf2014-03-071-0/+30
* Some minor code cleanups in freduce commandClifford Wolf2014-03-071-5/+5
* Added freduce -dumpClifford Wolf2014-03-061-1/+24
* Added freduce -stopClifford Wolf2014-03-061-3/+18
* fixed freduce for Minisat::SimpSolver: use frozen_literal()Clifford Wolf2014-03-031-2/+2
* Improved performance of freduce input cone reductionClifford Wolf2014-01-041-23/+78
* Improved freduce performance on const signalsClifford Wolf2014-01-041-13/+63
* Performance improvements in freduce passClifford Wolf2014-01-031-27/+69
* More freduce cleanupsClifford Wolf2014-01-031-0/+24
* Cleanups in freduce commandClifford Wolf2014-01-031-2/+5
* Use selection in freduce commandClifford Wolf2014-01-031-5/+20
* Another small freduce cleanup/bugfixClifford Wolf2014-01-031-1/+2
* More freduce cleanups and bugfixesClifford Wolf2014-01-031-11/+32
* Fixed more complex undef cases in freduceClifford Wolf2014-01-021-4/+36
* More "freduce" related fixes and improvementsClifford Wolf2014-01-021-19/+67
* Some cleanups in freduce -inv mode (and switched from -noinv to -inv)Clifford Wolf2014-01-021-26/+29
* Major rewrite of "freduce" commandClifford Wolf2014-01-021-279/+333
* freduce performance fixClifford Wolf2013-08-101-4/+8
* Added -try option to freduce passClifford Wolf2013-08-081-16/+44
* Fixed topological ordering in freduce passClifford Wolf2013-08-071-54/+67
* Small bugfixes in freduce passClifford Wolf2013-08-061-4/+14