iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
*	Add #include needed to build with gcc-11	Gabriel Somlo	2020-11-26	1	-0/+1
*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-2/+2
*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-1/+1
*	kernel: use more ID::*	Eddie Hung	2020-04-02	1	-4/+4
*	Further clean up `passes/sat/freduce.cc`.	Alberto Gonzalez	2020-03-30	1	-3/+2
*	Clean up pseudo-private member usage in `passes/sat/freduce.cc`.	Alberto Gonzalez	2020-03-28	1	-13/+12
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Add "setundef -anyseq"	Clifford Wolf	2017-05-28	1	-1/+2
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-1/+1
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-5/+5
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Added logic-loop error handling to freduce	Clifford Wolf	2015-06-30	1	-0/+11
*	Replaced ezDefaultSAT with ezSatPtr	Clifford Wolf	2015-02-21	1	-27/+27
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-3/+3
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-2/+2
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-3/+3
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-7/+7
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-7/+7
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-4/+1
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-5/+5
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-1/+1
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-2/+2
*	Fixed bug in freduce command	Clifford Wolf	2014-03-07	1	-0/+30
*	Some minor code cleanups in freduce command	Clifford Wolf	2014-03-07	1	-5/+5
*	Added freduce -dump	Clifford Wolf	2014-03-06	1	-1/+24
*	Added freduce -stop	Clifford Wolf	2014-03-06	1	-3/+18
*	fixed freduce for Minisat::SimpSolver: use frozen_literal()	Clifford Wolf	2014-03-03	1	-2/+2
*	Improved performance of freduce input cone reduction	Clifford Wolf	2014-01-04	1	-23/+78
*	Improved freduce performance on const signals	Clifford Wolf	2014-01-04	1	-13/+63
*	Performance improvements in freduce pass	Clifford Wolf	2014-01-03	1	-27/+69
*	More freduce cleanups	Clifford Wolf	2014-01-03	1	-0/+24
*	Cleanups in freduce command	Clifford Wolf	2014-01-03	1	-2/+5
*	Use selection in freduce command	Clifford Wolf	2014-01-03	1	-5/+20
*	Another small freduce cleanup/bugfix	Clifford Wolf	2014-01-03	1	-1/+2
*	More freduce cleanups and bugfixes	Clifford Wolf	2014-01-03	1	-11/+32
*	Fixed more complex undef cases in freduce	Clifford Wolf	2014-01-02	1	-4/+36
*	More "freduce" related fixes and improvements	Clifford Wolf	2014-01-02	1	-19/+67
*	Some cleanups in freduce -inv mode (and switched from -noinv to -inv)	Clifford Wolf	2014-01-02	1	-26/+29
*	Major rewrite of "freduce" command	Clifford Wolf	2014-01-02	1	-279/+333
*	freduce performance fix	Clifford Wolf	2013-08-10	1	-4/+8
*	Added -try option to freduce pass	Clifford Wolf	2013-08-08	1	-16/+44
*	Fixed topological ordering in freduce pass	Clifford Wolf	2013-08-07	1	-54/+67
*	Small bugfixes in freduce pass	Clifford Wolf	2013-08-06	1	-4/+14