iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	proc_prune: promote assigns to module connections when legal.	whitequark	2019-07-09	1	-20/+6
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	More flexible handling of initialization values	Clifford Wolf	2016-04-22	1	-7/+22
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Re-created command-reference-manual.tex, copied some doc fixes to online help	Clifford Wolf	2015-08-14	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-2/+6
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+1
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-5/+5
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-10/+9
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-2/+0
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-6/+6
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-6/+6
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	1	-0/+114