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* proc_prune: promote assigns to module connections when legal.whitequark2019-07-091-20/+6
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* More flexible handling of initialization valuesClifford Wolf2016-04-221-7/+22
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* namespace YosysClifford Wolf2014-09-271-2/+6
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+1
* Using new obj iterator API in a few placesClifford Wolf2014-07-271-5/+5
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-241-10/+9
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-2/+0
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-6/+6
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-6/+6
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-211-0/+114