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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Add warnings for driver-driver conflicts between FFs (and other cells) and co...Clifford Wolf2017-12-121-2/+3
* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-141-7/+19
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Added log_warning() APIClifford Wolf2014-11-091-2/+2
* namespace YosysClifford Wolf2014-09-271-5/+9
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-44/+44
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-3/+3
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-2/+1
* Using new obj iterator API in a few placesClifford Wolf2014-07-271-6/+6
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+4
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-45/+45
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-45/+45
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-52/+13
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-241-1/+1
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-4/+0
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-41/+41
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-41/+41
* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-211-10/+10
* Do not create $dffsr cells with no-op resets in proc_dffClifford Wolf2014-06-191-0/+5
* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-241-4/+115
* Improved handling of dff with async resetsClifford Wolf2013-10-211-5/+60
* Added dffsr support to proc_dff passClifford Wolf2013-10-181-7/+72
* fixed typosJohann Glaser2013-03-181-2/+2
* Added help messages to proc_* passesClifford Wolf2013-03-011-6/+18
* initial importClifford Wolf2013-01-051-0/+178