iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	rtlil: Make Process handling more uniform with Cell and Wire.	Marcelina Kościelnicka	2021-07-12	1	-5/+4
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
*	Add support for memory writes in processes.	Marcelina Kościelnicka	2021-03-08	1	-1/+1
*	proc_clean: Fix empty case removal conditions.	Marcelina Kościelnicka	2021-03-06	1	-10/+21
*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-2/+2
*	proc_clean: fix order of switch insertion.	whitequark	2019-08-19	1	-2/+1
*	proc_clean: add -quiet option.	whitequark	2019-07-09	1	-8/+24
*	proc_clean: fix critical typo.	whitequark	2019-01-23	1	-1/+1
*	proc_clean: fix fully def check to consider compare/signal length.	whitequark	2019-01-18	1	-1/+7
*	proc_clean: remove any empty cases if all cases use all-def compare.	whitequark	2018-12-23	1	-6/+28
*	proc_clean: remove any empty cases at the end of the switch.	whitequark	2018-12-22	1	-7/+3
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-2/+13
*	Fixed handling of constant-true branches in proc_clean	Clifford Wolf	2014-08-12	1	-1/+2
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-1/+1
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-8/+8
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-4/+4
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-4/+4
*	Added handling of multiple async paths in proc_arst	Clifford Wolf	2013-10-19	1	-8/+9
*	Added help messages to proc_* passes	Clifford Wolf	2013-03-01	1	-1/+15
*	initial import	Clifford Wolf	2013-01-05	1	-0/+160