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proc
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proc_arst.cc
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Author
Age
Files
Lines
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-22
/
+22
*
Fixed all users of SigSpec::chunks_rw() and removed it
Clifford Wolf
2014-07-23
1
-5
/
+3
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
1
-1
/
+1
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
1
-9
/
+9
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
1
-9
/
+9
*
Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst
Clifford Wolf
2014-02-21
1
-2
/
+6
*
Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
1
-2
/
+2
*
Added "proc_arst -global_arst" feature
Clifford Wolf
2013-11-20
1
-5
/
+59
*
Added handling of multiple async paths in proc_arst
Clifford Wolf
2013-10-19
1
-0
/
+12
*
Added nosync attribute and some async reset related fixes
Clifford Wolf
2013-03-25
1
-0
/
+5
*
Added help messages to proc_* passes
Clifford Wolf
2013-03-01
1
-6
/
+19
*
initial import
Clifford Wolf
2013-01-05
1
-0
/
+191