iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc	Eddie Hung	2019-09-01	1	-5/+0
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\| *	Do not restrict multiplier to unsigned	Eddie Hung	2019-08-30	1	-5/+0
* \|	Missing dep for test_pmgen	Eddie Hung	2019-08-30	1	-1/+1
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*	Cleanup	Eddie Hung	2019-08-28	1	-4/+0
*	Account for D port being a constant	Eddie Hung	2019-08-28	1	-4/+4
*	No need to replace Q of slice since $shiftx is autoremove-d	Eddie Hung	2019-08-28	1	-1/+0
*	More cleanup	Eddie Hung	2019-08-28	1	-12/+14
*	More cleanup	Eddie Hung	2019-08-28	1	-9/+6
*	Do not use default_params dict, hardcode default values, cleanup	Eddie Hung	2019-08-28	2	-25/+21
*	Always generate if no match	Eddie Hung	2019-08-28	1	-1/+1
*	Rename test_pmgen arg xilinx_srl.{fixed,variable}	Eddie Hung	2019-08-28	1	-2/+2
*	Missing close bracket	Eddie Hung	2019-08-26	1	-1/+1
*	Remove leftover header	Eddie Hung	2019-08-26	1	-1/+0
*	Improve xilinx_srl.fixed generate, add .variable generate	Eddie Hung	2019-08-26	1	-26/+75
*	Account for maxsubcnt overflowing	Eddie Hung	2019-08-26	1	-1/+1
*	Add xilinx_srl_pm.variable to test_pmgen	Eddie Hung	2019-08-26	1	-0/+2
*	Populate generate for xilinx_srl.fixed pattern	Eddie Hung	2019-08-26	1	-22/+54
*	Add xilinx_srl_fixed, fix typos	Eddie Hung	2019-08-26	1	-2/+6
*	Create new $__XILINX_SHREG_ cell for variable length too	Eddie Hung	2019-08-23	1	-31/+30
*	Do not allow Q of last cell of variable length SRL to be (* keep *)	Eddie Hung	2019-08-23	1	-0/+1
*	Also add first.Q to chain_bits since variable length	Eddie Hung	2019-08-23	1	-0/+1
*	Do not enforce !EN_POLARITY on $dffe	Eddie Hung	2019-08-23	1	-2/+0
*	Create new cell for fixed length SRL	Eddie Hung	2019-08-23	1	-14/+22
*	Cleanup FDRE matching	Eddie Hung	2019-08-23	1	-45/+19
*	Oops don't need a finally block	Eddie Hung	2019-08-23	1	-5/+0
*	Keep track of bits in variable length chain, to check for taps	Eddie Hung	2019-08-23	1	-0/+12
*	Don't forget $dff has no EN	Eddie Hung	2019-08-23	1	-2/+4
*	Same for variable length	Eddie Hung	2019-08-23	1	-2/+10
*	Filter on en_port for fixed length	Eddie Hung	2019-08-23	1	-4/+24
*	Check clock is consistent	Eddie Hung	2019-08-23	1	-5/+25
*	Fix last_cell.D	Eddie Hung	2019-08-23	1	-2/+1
*	Revert "Add a unique argument to pmgen's nusers()"	Eddie Hung	2019-08-23	1	-8/+4
*	Revert "Fix polarity"	Eddie Hung	2019-08-23	1	-1/+1
*	Fix polarity	Eddie Hung	2019-08-23	1	-1/+1
*	Check for non unique nusers/fanouts	Eddie Hung	2019-08-23	1	-2/+2
*	Add a unique argument to pmgen's nusers()	Eddie Hung	2019-08-23	1	-4/+8
*	Update doc	Eddie Hung	2019-08-23	1	-12/+19
*	Remove (* init *) entry when consumed into SRL	Eddie Hung	2019-08-23	1	-2/+6
*	indo -> into	Eddie Hung	2019-08-23	1	-1/+1
*	Forgot to slice	Eddie Hung	2019-08-23	1	-1/+2
*	Cope with possibility that D could connect to Q on same cell	Eddie Hung	2019-08-23	1	-1/+1
*	xilinx_srl to use 'slice' features of pmgen for word level	Eddie Hung	2019-08-23	2	-32/+49
*	Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl	Eddie Hung	2019-08-23	4	-34/+279
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\| *	Fix port hanlding in pmgen	Clifford Wolf	2019-08-23	1	-4/+3
\| *	Add pmgen slices and choices	Clifford Wolf	2019-08-23	4	-28/+276
* \|	Add doc	Eddie Hung	2019-08-22	1	-1/+14
* \|	Add copyright	Eddie Hung	2019-08-22	1	-0/+1
* \|	pmgen to also iterate over all module ports	Eddie Hung	2019-08-22	1	-2/+4
* \|	Remove output_bits	Eddie Hung	2019-08-22	2	-16/+7
* \|	Forgot to set ud_variable.minlen	Eddie Hung	2019-08-22	1	-0/+1