| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix #1462, #1480. | Marcin Kościelnicki | 2019-11-19 | 2 | -9/+11 |
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| * | Makefile: don't assume python is called `python3` | Sean Cross | 2019-10-19 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io> | ||||
| * | Fix dffmux peepopt init handling | Clifford Wolf | 2019-10-16 | 2 | -27/+113 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Move GENERATE_PATTERN macro to separate utility header | Clifford Wolf | 2019-10-16 | 3 | -128/+157 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Disable left-over log_debug in peepopt_dffmux.pmg | Clifford Wolf | 2019-10-16 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge pull request #1432 from YosysHQ/eddie/fix1427 | Eddie Hung | 2019-10-08 | 1 | -47/+81 |
| |\ | | | | | Refactor peepopt_dffmux and be sensitive to \init when trimming | ||||
| | * | Fix broken CI, check reset even for constants, trim rstmux | Eddie Hung | 2019-10-02 | 1 | -23/+26 |
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| | * | Refactor peepopt_dffmux and be sensitive to \init when trimming | Eddie Hung | 2019-10-02 | 1 | -32/+63 |
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| * | | Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments | Eddie Hung | 2019-10-08 | 4 | -68/+356 |
| |\ \ | | | | | | | Add notes and comments for xilinx_dsp | ||||
| | * | | Missed this | Eddie Hung | 2019-10-05 | 1 | -3/+4 |
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| | * | | Add comment on why we have to match for clock-enable/reset muxes | Eddie Hung | 2019-10-05 | 3 | -3/+11 |
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| | * | | Add note on pattern detector | Eddie Hung | 2019-10-05 | 1 | -3/+7 |
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| | * | | Add comments for xilinx_dsp_cascade | Eddie Hung | 2019-10-04 | 1 | -12/+100 |
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| | * | | Improve comments for xilinx_dsp_CREG | Eddie Hung | 2019-10-04 | 1 | -6/+7 |
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| | * | | Fix comment | Eddie Hung | 2019-10-04 | 1 | -1/+1 |
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| | * | | Restore optimisation for sigM.empty() | Eddie Hung | 2019-10-04 | 1 | -1/+4 |
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| | * | | Retry on fixing TODOs | Eddie Hung | 2019-10-04 | 2 | -13/+1 |
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| | * | | Revert "Fix TODOs" | Eddie Hung | 2019-10-04 | 2 | -0/+20 |
| | | | | | | | | | | | | | This reverts commit 8674a6c68d563908014d16671567459499c6dc99. | ||||
| | * | | More comments, cleanup | Eddie Hung | 2019-10-04 | 2 | -41/+108 |
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| | * | | Fix TODOs | Eddie Hung | 2019-10-04 | 2 | -20/+0 |
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| | * | | Consistency | Eddie Hung | 2019-10-04 | 1 | -3/+3 |
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| | * | | Add comments for xilinx_dsp | Eddie Hung | 2019-10-04 | 3 | -6/+134 |
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| * | | | Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarry | Clifford Wolf | 2019-10-06 | 1 | -0/+4 |
| |\ \ \ | | | | | | | | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf | ||||
| | * | | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf | Eddie Hung | 2019-10-05 | 1 | -0/+4 |
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| * | | | Update README.md | Clifford Wolf | 2019-10-05 | 1 | -1/+1 |
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| * | | | Merge pull request #1436 from YosysHQ/mmicko/msvc_fix | Miodrag Milanović | 2019-10-05 | 1 | -0/+1 |
| |\ \ \ | |/ / |/| | | Fixes for MSVC build | ||||
| | * | | Fixes for MSVC build | Miodrag Milanovic | 2019-10-04 | 1 | -0/+1 |
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| * / | Fix xilinx_dsp for unsigned extensions | Eddie Hung | 2019-10-04 | 1 | -1/+3 |
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| * | Ooops AREG and BREG to default to -1 | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
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| * | Update doc with max cascade chain of 20 | Eddie Hung | 2019-09-26 | 1 | -2/+4 |
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| * | Do not always zero out C (e.g. during cascade breaks) | Eddie Hung | 2019-09-26 | 2 | -7/+3 |
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| * | Update doc | Eddie Hung | 2019-09-26 | 1 | -1/+2 |
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| * | Zero out ports | Eddie Hung | 2019-09-26 | 1 | -2/+2 |
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| * | xilinx_dsp_cascade to also cascade AREG and BREG | Eddie Hung | 2019-09-26 | 2 | -454/+172 |
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| * | Try recursive pmgen for P cascade | Eddie Hung | 2019-09-26 | 1 | -88/+118 |
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| * | CREG to check for \keep | Eddie Hung | 2019-09-26 | 1 | -0/+3 |
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| * | Remove newline | Eddie Hung | 2019-09-26 | 1 | -1/+0 |
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| * | Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed) | Eddie Hung | 2019-09-25 | 1 | -1/+5 |
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| * | Reject if (* init *) present | Eddie Hung | 2019-09-25 | 2 | -0/+6 |
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| * | Rework xilinx_dsp postAdd for new wreduce call | Eddie Hung | 2019-09-25 | 1 | -3/+3 |
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| * | Fix memory issue since SigSpec& could be invalidated | Eddie Hung | 2019-09-25 | 1 | -6/+10 |
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| * | unextend only used in init | Eddie Hung | 2019-09-25 | 1 | -2/+1 |
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| * | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 1 | -5/+4 |
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| * | Set [AB]CASCREG to legal values | Eddie Hung | 2019-09-23 | 1 | -6/+10 |
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| * | Comment to explain separating CREG packing | Eddie Hung | 2019-09-23 | 1 | -0/+8 |
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| * | Separate out CREG packing into new pattern, to avoid conflict with PREG | Eddie Hung | 2019-09-23 | 4 | -46/+273 |
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| * | Move log_debug("\n") later | Eddie Hung | 2019-09-23 | 1 | -1/+1 |
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| * | Move unextend initialisation later | Eddie Hung | 2019-09-23 | 1 | -12/+9 |
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| * | Use new port() overload once more | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
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| * | Use new port/param overload in pmg | Eddie Hung | 2019-09-20 | 4 | -22/+22 |
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