iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Improve ice40_dsp for non-fully-32-bit adders	Eddie Hung	2019-08-09	1	-3/+8
*	Another filter -> if	Eddie Hung	2019-08-09	1	-2/+2
*	Cleanup	Eddie Hung	2019-08-09	2	-18/+18
*	Pack partial-product adder DSP48E1 packing	Eddie Hung	2019-08-09	2	-10/+79
*	Fix check	Eddie Hung	2019-08-09	1	-4/+6
*	Revert "Fix typo"	Eddie Hung	2019-08-09	1	-1/+1
*	Remove muxY and ffY for now	Eddie Hung	2019-08-08	2	-35/+33
*	Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing	Eddie Hung	2019-08-08	3	-39/+83
*	Only pack registers if {A,B,P}REG = 0, do not pack $dffe	Eddie Hung	2019-08-08	1	-3/+6
*	Disable $dffe	Eddie Hung	2019-08-08	1	-8/+8
*	Fix compile error	Eddie Hung	2019-08-07	1	-2/+2
*	Do not SigSpec::extract() beyond bounds	Eddie Hung	2019-08-07	2	-8/+10
*	Do not pack registers if (* keep *)	Eddie Hung	2019-08-07	1	-0/+20
*	Add comment about supporting $dffe in ice40_dsp	Eddie Hung	2019-08-01	1	-0/+1
*	Pack P register properly	Eddie Hung	2019-08-01	1	-2/+4
*	Cope with sign extension in mul2dsp	Eddie Hung	2019-08-01	2	-14/+14
*	CO is sign extension only if signed multiplier	Eddie Hung	2019-08-01	1	-1/+6
*	Fix typo	Eddie Hung	2019-08-01	1	-1/+1
*	Restore old CO behaviour	Eddie Hung	2019-07-31	1	-6/+7
*	Pop the CO bit from O	Eddie Hung	2019-07-26	1	-1/+3
*	Allow adders/accumulators with 33 bits using CO output	Eddie Hung	2019-07-26	1	-3/+8
*	Eliminate warnings by sizing O correctly	Eddie Hung	2019-07-23	1	-1/+5
*	Fix muxAB logic	Eddie Hung	2019-07-23	1	-3/+2
*	Remove debug print	Eddie Hung	2019-07-23	1	-1/+1
*	Simplify and fix for MACs	Eddie Hung	2019-07-23	2	-56/+38
*	Fix typo	Eddie Hung	2019-07-23	1	-13/+21
*	Fix spacing	Eddie Hung	2019-07-22	1	-2/+2
*	Pack hi and lo registers separately	Eddie Hung	2019-07-22	2	-39/+70
*	Rename according to vendor doc TN1295	Eddie Hung	2019-07-22	2	-55/+55
*	Pack Y register	Eddie Hung	2019-07-22	2	-22/+38
*	Pack adders not just accumulators	Eddie Hung	2019-07-22	2	-16/+33
*	Restore old ffY behaviour	Eddie Hung	2019-07-19	1	-16/+5
*	Cleanup	Eddie Hung	2019-07-19	1	-5/+5
*	Fine tune ice40_dsp.pmg, add support for packing subsets of registers	Eddie Hung	2019-07-19	4	-35/+47
*	Add support for ice40 signed multipliers	Eddie Hung	2019-07-19	1	-13/+8
*	ice40_dsp to accept $__MUL16X16 too	Eddie Hung	2019-07-18	1	-1/+1
*	Check if RHS is empty first	Eddie Hung	2019-07-18	1	-0/+2
*	Do not autoremove ffP aor muxP	Eddie Hung	2019-07-18	1	-2/+0
*	Improve pattern matcher to match subsets of $dffe? cells	Eddie Hung	2019-07-18	2	-12/+22
*	Improve A/B reg packing	Eddie Hung	2019-07-18	2	-6/+11
*	Do not autoremove A/B registers since they might have other consumers	Eddie Hung	2019-07-18	1	-2/+0
*	Fix xilinx_dsp index cast	Eddie Hung	2019-07-18	1	-2/+2
*	Wrong wildcard symbol	Eddie Hung	2019-07-18	1	-1/+1
*	Pattern matcher to check pool of bits, not exactly	Eddie Hung	2019-07-17	2	-5/+11
*	Signed extension	Eddie Hung	2019-07-16	2	-6/+6
*	Add support {A,B,P}REG packing	Eddie Hung	2019-07-16	2	-55/+94
*	Oops forgot these files	Eddie Hung	2019-07-15	1	-2/+7
*	Add xilinx_dsp for register packing	Eddie Hung	2019-07-15	3	-2/+192
*	Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047	Clifford Wolf	2019-05-28	1	-4/+11
*	Bugfix in peepopt_shiftmul.pmg	Clifford Wolf	2019-05-06	1	-0/+4