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* Perform D replacement properlyEddie Hung2019-09-061-5/+0
* Add support for DREGEddie Hung2019-09-061-2/+57
* Fine tune nusers when postAddEddie Hung2019-09-061-3/+3
* Fix macc and mul testsEddie Hung2019-09-061-3/+17
* Fix enable polarityEddie Hung2019-09-061-12/+12
* Add support for pre-adder and AD registerEddie Hung2019-09-061-3/+98
* Use more index patternsEddie Hung2019-09-061-15/+19
* Fix ffPmux to cope with offsetEddie Hung2019-09-061-12/+34
* Simplify filter expressionsEddie Hung2019-09-061-6/+12
* Fix nusers condition in ffPEddie Hung2019-09-061-2/+5
* Check adder is <= 48 bits before packingEddie Hung2019-09-061-4/+5
* Check nusers for M and P enable muxesEddie Hung2019-09-061-2/+17
* More nusers() checks for A and B enable muxesEddie Hung2019-09-061-14/+27
* Sensitive to CEB CEM CEP polarityEddie Hung2019-09-051-16/+19
* ffAmuxAB -> ffAenpolEddie Hung2019-09-051-4/+6
* Do not check signedness of post-adder (assume taken care of by DSP)Eddie Hung2019-09-051-1/+0
* Use filter instead of index; support wide enable muxesEddie Hung2019-09-051-4/+8
* Do not make ff[MP]mux semioptional, use sigmapEddie Hung2019-09-051-3/+6
* Add support for CEPEddie Hung2019-09-051-2/+20
* Add support for CEB, remove check on nusersEddie Hung2019-09-051-8/+20
* CleanupEddie Hung2019-09-051-5/+2
* Support CEAEddie Hung2019-09-051-3/+23
* Get rid of sigBset tooEddie Hung2019-09-041-8/+10
* Get rid of sigAsetEddie Hung2019-09-041-10/+14
* Get rid of sigPusedEddie Hung2019-09-041-14/+13
* Compute sigP properlyEddie Hung2019-09-041-1/+1
* Support CEMEddie Hung2019-09-041-5/+27
* Rename muxAB to postAddMuxEddie Hung2019-09-031-33/+14
* Use choices for addAB, now called postAddEddie Hung2019-09-031-40/+23
* Add support for load value into DSP48E1.PEddie Hung2019-09-031-29/+41
* Fine tune xilinx_dsp pattern matcherEddie Hung2019-08-301-14/+18
* Remove debugEddie Hung2019-08-301-1/+0
* Add support for ffMEddie Hung2019-08-301-3/+36
* New pmgen requires explicit acceptEddie Hung2019-08-301-0/+2
* xilinx_dsp to be sensitive to keep attributeEddie Hung2019-08-151-1/+14
* Perform C -> PCIN optimisation after pattern matcherEddie Hung2019-08-131-9/+15
* Check nusers of DSP output, not whole flopEddie Hung2019-08-091-1/+1
* CleanupEddie Hung2019-08-091-10/+10
* Pack partial-product adder DSP48E1 packingEddie Hung2019-08-091-5/+62
* Remove muxY and ffY for nowEddie Hung2019-08-081-30/+28
* Rework ice40_dsp to map to SB_MAC16 earlier, and check before packingEddie Hung2019-08-081-1/+1
* Only pack registers if {A,B,P}REG = 0, do not pack $dffeEddie Hung2019-08-081-3/+6
* Fine tune ice40_dsp.pmg, add support for packing subsets of registersEddie Hung2019-07-191-10/+10
* Check if RHS is empty firstEddie Hung2019-07-181-0/+2
* Improve pattern matcher to match subsets of $dffe? cellsEddie Hung2019-07-181-10/+14
* Improve A/B reg packingEddie Hung2019-07-181-6/+8
* Fix xilinx_dsp index castEddie Hung2019-07-181-2/+2
* Pattern matcher to check pool of bits, not exactlyEddie Hung2019-07-171-2/+2
* Signed extensionEddie Hung2019-07-161-4/+4
* Add support {A,B,P}REG packingEddie Hung2019-07-161-29/+52