Commit message (Collapse) | Author | Age | Files | Lines | |
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* | bugfix in opt_share | Clifford Wolf | 2014-12-28 | 1 | -0/+1 |
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* | Renamed hashmap.h to hashlib.h, some related improvements | Clifford Wolf | 2014-12-28 | 1 | -1/+1 |
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* | More hashtable finetuning | Clifford Wolf | 2014-12-27 | 1 | -1/+1 |
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* | Replaced std::unordered_map as implementation for Yosys::dict | Clifford Wolf | 2014-12-26 | 1 | -1/+1 |
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* | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -7/+11 |
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* | Added support for "keep" on modules | Clifford Wolf | 2014-09-29 | 1 | -1/+1 |
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* | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
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* | Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵ | Clifford Wolf | 2014-09-01 | 1 | -1/+1 |
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* | Added design->scratchpad | Clifford Wolf | 2014-08-30 | 1 | -2/+2 |
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* | RIP $safe_pmux | Clifford Wolf | 2014-08-14 | 1 | -1/+0 |
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* | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -4/+4 |
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* | Replaced sha1 implementation | Clifford Wolf | 2014-08-01 | 1 | -6/+1 |
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* | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -3/+3 |
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* | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -1/+0 |
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* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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* | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
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* | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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* | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
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* | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -8/+8 |
| | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||||
* | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -8/+8 |
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* | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -2/+1 |
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* | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
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* | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
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* | Improved handling of reg init in opt_share and opt_rmdff | Clifford Wolf | 2014-02-04 | 1 | -0/+19 |
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* | Improved opt_share for reduce cells | Clifford Wolf | 2013-03-29 | 1 | -0/+20 |
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* | Improved opt_share for commutative standard cells | Clifford Wolf | 2013-03-29 | 1 | -1/+28 |
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* | Added help messages for opt_* passes | Clifford Wolf | 2013-03-01 | 1 | -1/+14 |
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* | Moved stand-alone libs to libs/ directory and added libs/subcircuit | Clifford Wolf | 2013-02-27 | 1 | -1/+1 |
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* | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+250 |