Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Add flooring division operator | Xiretza | 2020-05-28 | 1 | -2/+2 |
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor. | ||||
* | Add flooring modulo operator | Xiretza | 2020-05-28 | 1 | -2/+2 |
| | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor. | ||||
* | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -16/+16 |
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* | opt_share: Fix handling of fine cells. | Marcin Kościelnicki | 2019-11-27 | 1 | -4/+11 |
| | | | | Fixes #1525. | ||||
* | passes: opt_share: don't statically initialize mergeable_type_map | Sean Cross | 2019-09-09 | 1 | -3/+4 |
| | | | | | | | | | | | | In 3d3779b0376b8204ed7637053176a07b7271ac1d this got turned from a `std::map<std::string, std::string>` to `std::map<IdString, IdString>`. Consequently, this exposed some initialization sequencing issues (#1361). Only initialize the map when it's first used, to avoid these static issues. This fixes #1361. Signed-off-by: Sean Cross <sean@xobs.io> | ||||
* | ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc | Eddie Hung | 2019-08-19 | 1 | -30/+30 |
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* | Use ID() macro | Eddie Hung | 2019-08-16 | 1 | -118/+110 |
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* | Fix wrong results when opt_share called before opt_clean | Bogdan Vukobratovic | 2019-08-07 | 1 | -18/+14 |
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* | Support various binary operators in opt_share | Bogdan Vukobratovic | 2019-08-04 | 1 | -194/+392 |
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* | Fix spacing in opt_share tests, change wording in opt_share help | Bogdan Vukobratovic | 2019-08-03 | 1 | -6/+10 |
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* | Reimplement opt_share to work on $alu and $pmux | Bogdan Vukobratovic | 2019-07-28 | 1 | -95/+225 |
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* | Implement opt_share | Bogdan Vukobratovic | 2019-07-26 | 1 | -0/+329 |
| | | | | | | This pass identifies arithmetic operators that share an operand and whose results are used in mutually exclusive cases controlled by a multiplexer, and merges them together by multiplexing the other operands | ||||
* | Renamed opt_share to opt_merge | Clifford Wolf | 2016-03-31 | 1 | -341/+0 |
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* | Bugfix for cell hash cache option in opt_share. | Mingyu Gao | 2015-08-11 | 1 | -0/+2 |
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* | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
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* | Added opt_share -share_all | Clifford Wolf | 2015-05-31 | 1 | -10/+21 |
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* | Using design->selected_modules() in opt_* | Clifford Wolf | 2015-02-03 | 1 | -4/+2 |
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* | bugfix in opt_share | Clifford Wolf | 2014-12-28 | 1 | -0/+1 |
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* | Renamed hashmap.h to hashlib.h, some related improvements | Clifford Wolf | 2014-12-28 | 1 | -1/+1 |
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* | More hashtable finetuning | Clifford Wolf | 2014-12-27 | 1 | -1/+1 |
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* | Replaced std::unordered_map as implementation for Yosys::dict | Clifford Wolf | 2014-12-26 | 1 | -1/+1 |
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* | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -7/+11 |
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* | Added support for "keep" on modules | Clifford Wolf | 2014-09-29 | 1 | -1/+1 |
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* | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
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* | Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵ | Clifford Wolf | 2014-09-01 | 1 | -1/+1 |
| | | | | RTLIL::SigChunk::data | ||||
* | Added design->scratchpad | Clifford Wolf | 2014-08-30 | 1 | -2/+2 |
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* | RIP $safe_pmux | Clifford Wolf | 2014-08-14 | 1 | -1/+0 |
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* | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -4/+4 |
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* | Replaced sha1 implementation | Clifford Wolf | 2014-08-01 | 1 | -6/+1 |
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* | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -3/+3 |
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* | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -1/+0 |
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* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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* | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
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* | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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* | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
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* | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -8/+8 |
| | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||||
* | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -8/+8 |
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* | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -2/+1 |
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* | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
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* | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
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* | Improved handling of reg init in opt_share and opt_rmdff | Clifford Wolf | 2014-02-04 | 1 | -0/+19 |
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* | Improved opt_share for reduce cells | Clifford Wolf | 2013-03-29 | 1 | -0/+20 |
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* | Improved opt_share for commutative standard cells | Clifford Wolf | 2013-03-29 | 1 | -1/+28 |
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* | Added help messages for opt_* passes | Clifford Wolf | 2013-03-01 | 1 | -1/+14 |
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* | Moved stand-alone libs to libs/ directory and added libs/subcircuit | Clifford Wolf | 2013-02-27 | 1 | -1/+1 |
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* | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+250 |