iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-3/+3
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-26/+26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-26/+26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-2/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-7/+7
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-7/+7
*	Fixed detection of init attribute in opt_rmdff	Clifford Wolf	2014-02-04	1	-1/+1
*	Improved handling of reg init in opt_share and opt_rmdff	Clifford Wolf	2014-02-04	1	-7/+29
*	Added constant-clock case to opt_rmdff	Clifford Wolf	2014-02-02	1	-0/+8
*	Added support for $adff with undef data inputs to opt_rmdff	Clifford Wolf	2014-01-17	1	-0/+6
*	Added log_abort() api	Clifford Wolf	2013-05-24	1	-1/+1
*	Some improvements in opt_rmdff	Clifford Wolf	2013-05-23	1	-2/+33
*	Added help messages for opt_* passes	Clifford Wolf	2013-03-01	1	-1/+16
*	initial import	Clifford Wolf	2013-01-05	1	-0/+135