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passes
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opt
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opt_reduce.cc
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Author
Age
Files
Lines
*
Add v2 memory cells.
Marcelina KoĆcielnicka
2021-08-11
1
-2
/
+2
*
Fixing old e-mail addresses and deadnames
Claire Xenia Wolf
2021-06-08
1
-1
/
+1
*
Use C++11 final/override keywords.
whitequark
2020-06-18
1
-2
/
+2
*
kernel: big fat patch to use more ID::*, otherwise ID(*)
Eddie Hung
2020-04-02
1
-14
/
+14
*
kernel: SigSpec use more const& + overloads to prevent implicit SigSpec
Eddie Hung
2020-03-13
1
-4
/
+4
*
Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys
Claire Wolf
2020-01-29
1
-1
/
+3
|
\
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*
Fix input vector for reduce cells. Infinite loop fixed.
Kaj Tuomi
2017-10-17
1
-0
/
+2
*
|
opt_reduce: Call check() per run rather than per optimised cell
David Shah
2020-01-28
1
-1
/
+2
*
|
Use more ID::{A,B,Y,blackbox,whitebox}
Eddie Hung
2019-08-15
1
-33
/
+33
*
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Use ID() macro in all of passes/opt/
Clifford Wolf
2019-08-11
1
-55
/
+55
*
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Consistent use of 'override' for virtual methods in derived classes.
Henner Zeller
2018-07-20
1
-2
/
+2
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/
*
Revert 90be0d8 as it causes endless loops for some designs
Clifford Wolf
2017-10-14
1
-1
/
+0
*
Fix input vector for reduce cells.
Kaj Tuomi
2017-10-12
1
-0
/
+1
*
Added "yosys -D" feature
Clifford Wolf
2016-04-21
1
-1
/
+1
*
Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
1
-1
/
+1
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
1
-3
/
+3
*
Using design->selected_modules() in opt_*
Clifford Wolf
2015-02-03
1
-7
/
+4
*
using dict and pool in opt_reduce
Clifford Wolf
2014-12-28
1
-5
/
+5
*
Added "opt -full" alias for all more aggressive optimizations
Clifford Wolf
2014-10-31
1
-0
/
+7
*
namespace Yosys
Clifford Wolf
2014-09-27
1
-0
/
+4
*
Added design->scratchpad
Clifford Wolf
2014-08-30
1
-4
/
+2
*
RIP $safe_pmux
Clifford Wolf
2014-08-14
1
-1
/
+1
*
Fixed a performance bug in opt_reduce
Clifford Wolf
2014-08-02
1
-2
/
+6
*
Replaced sha1 implementation
Clifford Wolf
2014-08-01
1
-1
/
+0
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
1
-40
/
+40
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
1
-1
/
+0
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
1
-1
/
+1
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
1
-5
/
+5
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
1
-4
/
+10
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
1
-39
/
+39
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-39
/
+39
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
1
-10
/
+3
*
Fixed memory corruption in "opt_reduce" pass
Clifford Wolf
2014-07-25
1
-5
/
+7
*
Removed RTLIL::SigSpec::expand() method
Clifford Wolf
2014-07-23
1
-17
/
+19
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
1
-14
/
+14
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
1
-14
/
+14
*
Added "opt_const -fine" and "opt_reduce -fine"
Clifford Wolf
2014-07-21
1
-5
/
+19
*
Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port
Clifford Wolf
2014-07-18
1
-0
/
+15
*
Improved opt_reduce handling of mem wr_en mux bits
Clifford Wolf
2014-07-17
1
-5
/
+18
*
improved opt_reduce for $mem/$memwr WR_EN multiplexers
Clifford Wolf
2014-07-16
1
-0
/
+80
*
Fixed bug in opt_reduce (see vloghammer issue_044)
Clifford Wolf
2014-05-12
1
-1
/
+4
*
Fixed undef handling in opt_reduce
Clifford Wolf
2014-03-06
1
-2
/
+2
*
Cleanups and bugfixes in response to new internal cell checker
Clifford Wolf
2013-11-11
1
-0
/
+1
*
Added help messages for opt_* passes
Clifford Wolf
2013-03-01
1
-1
/
+16
*
Moved stand-alone libs to libs/ directory and added libs/subcircuit
Clifford Wolf
2013-02-27
1
-1
/
+1
*
initial import
Clifford Wolf
2013-01-05
1
-0
/
+236