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* opt_reduce: Fix use-after-free.Marcelina Kościelnicka2022-07-231-4/+2
* opt_reduce: Add $bmux and $demux optimization patterns.Marcelina Kościelnicka2022-01-301-60/+337
* Add v2 memory cells.Marcelina Kościelnicka2021-08-111-2/+2
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-14/+14
* kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-131-4/+4
* Merge branch 'vector_fix' of https://github.com/Kmanfi/yosysClaire Wolf2020-01-291-1/+3
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| * Fix input vector for reduce cells. Infinite loop fixed.Kaj Tuomi2017-10-171-0/+2
* | opt_reduce: Call check() per run rather than per optimised cellDavid Shah2020-01-281-1/+2
* | Use more ID::{A,B,Y,blackbox,whitebox}Eddie Hung2019-08-151-33/+33
* | Use ID() macro in all of passes/opt/Clifford Wolf2019-08-111-55/+55
* | Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
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* Revert 90be0d8 as it causes endless loops for some designsClifford Wolf2017-10-141-1/+0
* Fix input vector for reduce cells.Kaj Tuomi2017-10-121-0/+1
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Using design->selected_modules() in opt_*Clifford Wolf2015-02-031-7/+4
* using dict and pool in opt_reduceClifford Wolf2014-12-281-5/+5
* Added "opt -full" alias for all more aggressive optimizationsClifford Wolf2014-10-311-0/+7
* namespace YosysClifford Wolf2014-09-271-0/+4
* Added design->scratchpadClifford Wolf2014-08-301-4/+2
* RIP $safe_pmuxClifford Wolf2014-08-141-1/+1
* Fixed a performance bug in opt_reduceClifford Wolf2014-08-021-2/+6
* Replaced sha1 implementationClifford Wolf2014-08-011-1/+0
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-40/+40
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-5/+5
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+10
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-39/+39
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-39/+39
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-10/+3
* Fixed memory corruption in "opt_reduce" passClifford Wolf2014-07-251-5/+7
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-17/+19
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-14/+14
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-14/+14
* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-211-5/+19
* Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN portClifford Wolf2014-07-181-0/+15
* Improved opt_reduce handling of mem wr_en mux bitsClifford Wolf2014-07-171-5/+18
* improved opt_reduce for $mem/$memwr WR_EN multiplexersClifford Wolf2014-07-161-0/+80
* Fixed bug in opt_reduce (see vloghammer issue_044)Clifford Wolf2014-05-121-1/+4
* Fixed undef handling in opt_reduceClifford Wolf2014-03-061-2/+2
* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-111-0/+1
* Added help messages for opt_* passesClifford Wolf2013-03-011-1/+16
* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-271-1/+1
* initial importClifford Wolf2013-01-051-0/+236