| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | using dict and pool in opt_reduce | Clifford Wolf | 2014-12-28 | 1 | -5/+5 |
| * | Added "opt -full" alias for all more aggressive optimizations | Clifford Wolf | 2014-10-31 | 1 | -0/+7 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
| * | Added design->scratchpad | Clifford Wolf | 2014-08-30 | 1 | -4/+2 |
| * | RIP $safe_pmux | Clifford Wolf | 2014-08-14 | 1 | -1/+1 |
| * | Fixed a performance bug in opt_reduce | Clifford Wolf | 2014-08-02 | 1 | -2/+6 |
| * | Replaced sha1 implementation | Clifford Wolf | 2014-08-01 | 1 | -1/+0 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -40/+40 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -1/+0 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -5/+5 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -4/+10 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -39/+39 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -39/+39 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -10/+3 |
| * | Fixed memory corruption in "opt_reduce" pass | Clifford Wolf | 2014-07-25 | 1 | -5/+7 |
| * | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 | 1 | -17/+19 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -14/+14 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -14/+14 |
| * | Added "opt_const -fine" and "opt_reduce -fine" | Clifford Wolf | 2014-07-21 | 1 | -5/+19 |
| * | Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port | Clifford Wolf | 2014-07-18 | 1 | -0/+15 |
| * | Improved opt_reduce handling of mem wr_en mux bits | Clifford Wolf | 2014-07-17 | 1 | -5/+18 |
| * | improved opt_reduce for $mem/$memwr WR_EN multiplexers | Clifford Wolf | 2014-07-16 | 1 | -0/+80 |
| * | Fixed bug in opt_reduce (see vloghammer issue_044) | Clifford Wolf | 2014-05-12 | 1 | -1/+4 |
| * | Fixed undef handling in opt_reduce | Clifford Wolf | 2014-03-06 | 1 | -2/+2 |
| * | Cleanups and bugfixes in response to new internal cell checker | Clifford Wolf | 2013-11-11 | 1 | -0/+1 |
| * | Added help messages for opt_* passes | Clifford Wolf | 2013-03-01 | 1 | -1/+16 |
| * | Moved stand-alone libs to libs/ directory and added libs/subcircuit | Clifford Wolf | 2013-02-27 | 1 | -1/+1 |
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+236 |
