iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Added memory_bram "make_outreg" feature	Clifford Wolf	2015-04-09	1	-2/+25
*	Added support for "file names with blanks"	Clifford Wolf	2015-04-08	1	-3/+1
*	Added support for initialized brams	Clifford Wolf	2015-04-06	1	-8/+35
*	Avoid parameter values with size 0 ($mem cells)	Clifford Wolf	2015-04-05	2	-6/+11
*	Replaced ezDefaultSAT with ezSatPtr	Clifford Wolf	2015-02-21	1	-7/+7
*	Various fixes for memories with offsets	Clifford Wolf	2015-02-14	2	-5/+17
*	Added $meminit support to "memory" command	Clifford Wolf	2015-02-14	3	-30/+69
*	Added onehot attribute	Clifford Wolf	2015-02-04	1	-0/+13
*	Fixed typos found by lintian	Ruben Undheim	2015-02-01	1	-2/+2
*	Refactoring of memory_bram and xilinx brams	Clifford Wolf	2015-01-18	1	-204/+407
*	memory_bram hotfix for memories with width 1	Clifford Wolf	2015-01-06	1	-3/+3
*	removed old debug code	Clifford Wolf	2015-01-06	1	-1/+0
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	1	-1/+0
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	1	-1/+1
*	Towards Xilinx bram support	Clifford Wolf	2015-01-05	1	-0/+3
*	Towards Xilinx bram support	Clifford Wolf	2015-01-04	1	-3/+4
*	Added memory_bram "shuffle_enable" feature	Clifford Wolf	2015-01-04	1	-1/+113
*	Removed left over debug code from memory_bram	Clifford Wolf	2015-01-04	1	-2/+2
*	Added "memory -bram"	Clifford Wolf	2015-01-03	1	-2/+11
*	Added memory_bram 'or_next_if_better' feature	Clifford Wolf	2015-01-03	1	-42/+156
*	memory_bram transp support	Clifford Wolf	2015-01-03	1	-4/+22
*	Progress in memory_bram	Clifford Wolf	2015-01-03	1	-11/+5
*	Added proper clkpol support to memory_bram	Clifford Wolf	2015-01-02	1	-4/+32
*	Progress in memory_bram	Clifford Wolf	2015-01-02	1	-3/+6
*	Progress in memory_bram	Clifford Wolf	2015-01-02	1	-1/+10
*	Progress in memory_bram	Clifford Wolf	2015-01-01	1	-22/+207
*	Progress in memory_bram	Clifford Wolf	2015-01-01	1	-37/+145
*	Progress in memory_bram	Clifford Wolf	2014-12-31	1	-7/+115
*	Added memory_bram (not functional yet)	Clifford Wolf	2014-12-31	2	-0/+286
*	More dict/pool related changes	Clifford Wolf	2014-12-27	1	-2/+2
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-12/+12
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-5/+5
*	namespace Yosys	Clifford Wolf	2014-09-27	6	-12/+32
*	Fixed $memwr/$memrd order in memory_dff	Clifford Wolf	2014-09-16	1	-4/+6
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-1/+1
*	Improved write address decoder generation memory_map	Clifford Wolf	2014-08-30	1	-16/+28
*	Using worker class in memory_map	Clifford Wolf	2014-08-30	1	-226/+231
*	Various improvements in memory_dff pass	Clifford Wolf	2014-08-06	1	-21/+22
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	3	-9/+9
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	1	-3/+2
*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31	1	-5/+6
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	5	-128/+128
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	4	-4/+4
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-0/+2
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	4	-15/+11
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-15/+11
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	5	-5/+5
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	5	-9/+9
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	2	-2/+2