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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-06 14:26:51 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-06 14:26:51 +0100 |
| commit | 081e1a49f81c298a5c30c4b51241d50ce64f185e (patch) | |
| tree | 8318a8a68cb21d9ea810bdb2554cfcc4e2b0b625 /passes/memory | |
| parent | 9c7f47bbd5fc190578054a6d018760c2f2b62c03 (diff) | |
| download | yosys-081e1a49f81c298a5c30c4b51241d50ce64f185e.tar.gz yosys-081e1a49f81c298a5c30c4b51241d50ce64f185e.tar.bz2 yosys-081e1a49f81c298a5c30c4b51241d50ce64f185e.zip | |
Towards Xilinx bram support
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_bram.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index e7a42f26d..fd5db188e 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -356,7 +356,7 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_ for (int i = 0; i < fillbits; i++) { for (int j = 0; j < wr_ports; j++) { new_wr_en[j].append(fillbit); - new_wr_data[j].append(State::Sx); + new_wr_data[j].append(State::S0); } for (int j = 0; j < rd_ports; j++) new_rd_data[j].append(State::Sx); |