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* Make liberal use of IdString.in()Eddie Hung2019-08-061-1/+1
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* memory_dff: Fix checking of feedback mux input when more than one muxDavid Shah2019-07-021-3/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix spacingEddie Hung2019-06-251-4/+3
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* Move only one consumer check outside of while loopEddie Hung2019-06-251-6/+5
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* Walk through as many muxes as exist for rd_enEddie Hung2019-06-241-8/+16
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* memory_dff: Fix typo when checking init valueDavid Shah2018-12-181-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Disable memory_dff for initialized FFsClifford Wolf2018-05-281-1/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
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* Fixed some visual studio warningsClifford Wolf2016-02-131-1/+1
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* Bugfix in memory_dffClifford Wolf2015-10-311-1/+12
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* Added read-enable to memory modelClifford Wolf2015-09-251-9/+43
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* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
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* Modernized memory_dff (and fixed a bug)Clifford Wolf2015-06-141-147/+164
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* Merge clock inverters in memory_dffClifford Wolf2015-06-091-16/+37
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* namespace YosysClifford Wolf2014-09-271-6/+10
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* Fixed $memwr/$memrd order in memory_dffClifford Wolf2014-09-161-4/+6
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* Various improvements in memory_dff passClifford Wolf2014-08-061-21/+22
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-19/+19
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-1/+1
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* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
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* Using new obj iterator API in a few placesClifford Wolf2014-07-271-15/+11
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-7/+2
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* Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+7
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-19/+19
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-19/+19
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-1/+0
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* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-8/+4
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-221-1/+1
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-6/+6
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-6/+6
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* Fixed log messages in memory_dffClifford Wolf2014-06-011-0/+2
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* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-28/+39
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* A fix in memory_dff for write ports with static addressesClifford Wolf2013-12-011-10/+10
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* Added help messages to memory_* passesClifford Wolf2013-03-011-3/+17
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* initial importClifford Wolf2013-01-051-0/+200