iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
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*	Fixed some visual studio warnings	Clifford Wolf	2016-02-13	1	-1/+1
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*	Bugfix in memory_dff	Clifford Wolf	2015-10-31	1	-1/+12
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*	Added read-enable to memory model	Clifford Wolf	2015-09-25	1	-9/+43
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
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*	Modernized memory_dff (and fixed a bug)	Clifford Wolf	2015-06-14	1	-147/+164
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*	Merge clock inverters in memory_dff	Clifford Wolf	2015-06-09	1	-16/+37
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*	namespace Yosys	Clifford Wolf	2014-09-27	1	-6/+10
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*	Fixed $memwr/$memrd order in memory_dff	Clifford Wolf	2014-09-16	1	-4/+6
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*	Various improvements in memory_dff pass	Clifford Wolf	2014-08-06	1	-21/+22
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-19/+19
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-1/+1
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-15/+11
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-3/+3
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-7/+2
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-4/+7
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-19/+19
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-19/+19
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-1/+0
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*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-8/+4
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22	1	-1/+1
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-6/+6
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-6/+6
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*	Fixed log messages in memory_dff	Clifford Wolf	2014-06-01	1	-0/+2
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-28/+39
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*	A fix in memory_dff for write ports with static addresses	Clifford Wolf	2013-12-01	1	-10/+10
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*	Added help messages to memory_* passes	Clifford Wolf	2013-03-01	1	-3/+17
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+200