Commit message (Expand) | Author | Age | Files | Lines | |
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* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
* | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
* | Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys | Clifford Wolf | 2014-03-11 | 1 | -1/+2 |
* | Replaced RTLIL::Const::str with generic decoder method | Clifford Wolf | 2013-12-04 | 1 | -6/+6 |
* | Improved FSM one-hot encoding, added binary encoding | Clifford Wolf | 2013-05-24 | 1 | -19/+46 |
* | Added help messages for fsm_* passes | Clifford Wolf | 2013-03-01 | 1 | -4/+19 |
* | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+114 |