| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -5/+5 |
| * | Changed from "and" to "&&" | William Speirs | 2014-10-15 | 1 | -1/+1 |
| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -3/+3 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -1/+9 |
| * | Some improvements in fsm_opt and fsm_map for FSM with unreachable states | Clifford Wolf | 2014-08-09 | 1 | -0/+44 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -7/+7 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -5/+9 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -8/+8 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -8/+8 |
| * | SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands | Clifford Wolf | 2014-07-22 | 1 | -8/+4 |
| * | fixed memory leak in fsm_opt | Clifford Wolf | 2014-07-22 | 1 | -1/+3 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -9/+9 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -9/+9 |
| * | Replaced RTLIL::Const::str with generic decoder method | Clifford Wolf | 2013-12-04 | 1 | -1/+1 |
| * | Renamed opt_rmunused to opt_clean | Clifford Wolf | 2013-06-05 | 1 | -1/+1 |
| * | Added help messages for fsm_* passes | Clifford Wolf | 2013-03-01 | 1 | -5/+17 |
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+285 |
