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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-20/+18
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* kernel: use more ID::*Eddie Hung2020-04-021-19/+19
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* Make liberal use of IdString.in()Eddie Hung2019-08-061-1/+1
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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Be more conservative with merging large cells into FSMsClifford Wolf2017-01-261-3/+17
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* Add warnings for quickly growing FSM table size in fsm_expandClifford Wolf2017-01-261-0/+10
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* Added "fsm_expand -full"Clifford Wolf2016-11-021-15/+25
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* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
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* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
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* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
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* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-111-1/+1
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* namespace YosysClifford Wolf2014-09-271-0/+4
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* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-151-4/+4
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* RIP $safe_pmuxClifford Wolf2014-08-141-1/+1
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-27/+27
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* Using log_assert() instead of assert()Clifford Wolf2014-07-281-3/+3
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-2/+2
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-8/+8
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* Manual fixes for new cell connections APIClifford Wolf2014-07-261-2/+6
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-28/+28
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-28/+28
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-4/+2
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* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-9/+9
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-9/+9
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* Some fixes to improve determinismClifford Wolf2013-08-091-4/+4
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* Improved method for finding fsm_expand candidatesClifford Wolf2013-03-251-5/+7
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* Changed fsm_expand to merge multiplexers more aggressivelyClifford Wolf2013-03-241-1/+4
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* fixed typosJohann Glaser2013-03-181-1/+1
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* Added help messages for fsm_* passesClifford Wolf2013-03-011-6/+19
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* initial importClifford Wolf2013-01-051-0/+255