| Commit message (Expand) | Author | Age | Files | Lines |
* | Clean up `passes/cmds/stat.cc`. | Alberto Gonzalez | 2020-04-06 | 1 | -26/+20 |
* | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -17/+17 |
* | kernel: use more ID::* | Eddie Hung | 2020-04-02 | 1 | -5/+5 |
* | Tweak default gate costs, cleanup "stat -tech cmos" | Clifford Wolf | 2019-08-07 | 1 | -16/+6 |
* | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 1 | -0/+4 |
* | Add "stat -tech cmos" | Clifford Wolf | 2019-07-20 | 1 | -2/+29 |
* | Fix typo | Clifford Wolf | 2019-06-20 | 1 | -2/+2 |
* | Add "stat -tech xilinx" | Clifford Wolf | 2019-05-11 | 1 | -3/+73 |
* | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
* | Include module name for area summary stats | Edmond Cote | 2018-06-18 | 1 | -4/+4 |
* | Add support for "yosys -E" | Clifford Wolf | 2018-01-07 | 1 | -0/+1 |
* | Add $alu to list of supported cells for "stat -width" | Clifford Wolf | 2017-07-14 | 1 | -1/+1 |
* | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
* | Added "stat -liberty" for calculating chip area | Clifford Wolf | 2016-02-04 | 1 | -6/+60 |
* | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -1/+1 |
* | improvement in "stat" | Clifford Wolf | 2015-10-24 | 1 | -1/+1 |
* | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
* | Fixed "stat" handling of blackbox modules | Clifford Wolf | 2015-02-14 | 1 | -9/+6 |
* | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -5/+5 |
* | sort cell types in "stat" output by name | Clifford Wolf | 2014-10-03 | 1 | -2/+2 |
* | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -113/+114 |
* | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 | 1 | -1/+1 |
* | Added "stat -width" | Clifford Wolf | 2014-08-22 | 1 | -4/+37 |
* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
* | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
* | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
* | Bugfixes in new "stat" command | Clifford Wolf | 2013-11-25 | 1 | -7/+1 |
* | Added "stat" command | Clifford Wolf | 2013-11-25 | 1 | -0/+218 |