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* Tweak default gate costs, cleanup "stat -tech cmos"Clifford Wolf2019-08-071-16/+6
* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+4
* Add "stat -tech cmos"Clifford Wolf2019-07-201-2/+29
* Fix typoClifford Wolf2019-06-201-2/+2
* Add "stat -tech xilinx"Clifford Wolf2019-05-111-3/+73
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Include module name for area summary statsEdmond Cote2018-06-181-4/+4
* Add support for "yosys -E"Clifford Wolf2018-01-071-0/+1
* Add $alu to list of supported cells for "stat -width"Clifford Wolf2017-07-141-1/+1
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Added "stat -liberty" for calculating chip areaClifford Wolf2016-02-041-6/+60
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
* improvement in "stat"Clifford Wolf2015-10-241-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Fixed "stat" handling of blackbox modulesClifford Wolf2015-02-141-9/+6
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-5/+5
* sort cell types in "stat" output by nameClifford Wolf2014-10-031-2/+2
* namespace YosysClifford Wolf2014-09-271-113/+114
* Removed $bu0 cell typeClifford Wolf2014-09-041-1/+1
* Added "stat -width"Clifford Wolf2014-08-221-4/+37
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-3/+3
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* Bugfixes in new "stat" commandClifford Wolf2013-11-251-7/+1
* Added "stat" commandClifford Wolf2013-11-251-0/+218