| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| * | Implemented "scc -set_attr" | Clifford Wolf | 2016-11-06 | 1 | -22/+32 |
| * | Bugfix in "scc" command | Clifford Wolf | 2016-11-06 | 1 | -9/+11 |
| * | Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop | Clifford Wolf | 2016-05-27 | 1 | -3/+3 |
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
| * | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -2/+2 |
| * | Some ASCII encoding fixes (comments and docs) by Larry Doolittle | Clifford Wolf | 2015-08-13 | 1 | -1/+1 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
| * | Added "scc -expect <N> -nofeedback" | Clifford Wolf | 2015-02-10 | 1 | -7/+48 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
| * | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 1 | -1/+1 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -3/+3 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
| * | Moved some passes to other source directories | Clifford Wolf | 2014-02-08 | 1 | -0/+299 |
